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CONTROL REGISTERS
IMR
— Interrupt Mask Register
Bit Identifier
Reset Value
Read/Write
Addressing Mode
.7
.6
.5
.4
.3
.2
.1
.0
NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.
4-16
.7
.6
x
x
R/W
R/W
Register addressing mode only
Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P1.4–1.7
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P1.3
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 5 (IRQ5) Enable Bit; External Interrupt P0.2
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 4 (IRQ4) Enable Bit; External Interrupt P0.1
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 3 (IRQ3) Enable Bit; External Interrupt P0.0
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 2 (IRQ2) Enable Bit; Watch Timer Overflow
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 1 (IRQ1) Enable Bit; SIO Interrupt
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 0 (IRQ0) Enable Bit; Timer 1/A Match, Timer B Match
0
Disable (mask)
1
Enable (unmask)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
.5
.4
x
x
R/W
R/W
R/W
DDH
.3
.2
.1
x
x
x
R/W
R/W
Set 1
.0
x
R/W
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