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CONTROL REGISTERS
EXTICONL
—
Bit Identifier
Reset Value
Read/Write
Addressing Mode
.7–.6
.5–.4
.3–.2
.1–.0
4-10
External Interrupt Control Register (Low Byte)
.7
.6
0
0
R/W
R/W
Register addressing mode only
P1.3 External Interrupt (INT3) Configuration Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P0.2 External Interrupt (INT2) Configuration Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P0.1 External Interrupt (INT1) Configuration Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P0.0 External Interrupt (INT0) Configuration Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
.5
.4
0
0
R/W
R/W
R/W
F9H
Set 1, Bank 0
.3
.2
.1
0
0
0
R/W
R/W
.0
0
R/W
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