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6: The Bus Interface
The AHB bus master interface signals are shown in Figure 6-2.
A rbiter grant
Transf er
response
Reset
Clock
Data
6-4
HGRANT
HREADY
HRESP[1:0]
HRESETn
A HB master
HCLK
HCLKEN
HRDATA[31:0]
Figure 6-2 AHB bus master interface
EPSON
HBUSREQ
A rbiter
HLOCK
HTRANS[1:0]
Transf er type
HADDR[31:0]
HWRITE
A ddress
HSIZE[2:0]
and control
HBURST[2:0]
HPROT[3:0]
HWDATA[31:0]
Data
ARM720T CORE CPU MANUAL
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