Table of Contents
Advertisement
Glossary
Complex Instruction Set Computer
A microprocessor that recognizes a large number of instructions.
See also
See
CPSR
The bottom eight bits of a program status register. The control bits change
Control bits
when an exception arises and can be altered by software only when the
processor is in a privileged mode.
Current Program Status Register
See
Debug Communications Channel.
DCC
A condition that allows the monitoring and control of the execution of a
Debug state
processor. Usually used to find errors in the application program flow. A
processor enters debug state from
A debugging system which includes a program, used to detect, locate, and
Debugger
correct software faults, together with custom hardware that supports
software debugging.
The EmbeddedICE logic is controlled via the JTAG test access port, using
EmbeddedICE
a protocol converter such as MultiICE: an extra piece of hardware that
allows software tools to debug code running on a target processor.
See also
EmbeddedICE-RT
A version of EmbeddedICE logic that has improved support for real-time
debugging.
Exception modes
Privileged modes that are entered when specific exceptions occur.
Handles an event. For example, an exception could handle an external
Exception
interrupt or an undefined instruction.
An abort that is generated by the external memory system.
External abort
Fast interrupt.
FIQ
Glossary-2
Reduced Instruction Set Computer.
Program Status Register.
Program Status Register.
ICE and JTAG.
halt mode
EPSON
monitor mode
and not from
ARM720T CORE CPU MANUAL
.
Advertisement
Table of Contents
