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1C307 DAT Signal Processor (CXD2601AQ)
error correction circuit, digital I/O, RAM control circuit, etc.
ele
A08, A09
VDD
Al0-A12
Al3, Al4
XWE
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J-2-0|-c001|-~~-
Description
RAM address A08, A09
5V
RAM address A10-A12
RAM address A13, Al4
RAM write enable signal
RAM output enable signal
External addressing bus interrupt enable signal (Not in use)
Test pin (normally "L")
18.816 MHz crystal oscillator output
18.816 MHz crystal oscillator input
GND
Reset pin (normally"H")
18.816 MHz clock output (Not in use)
SYEK (internal system clock) generation CLKO division timing signal (Not in use)
ATF sync signal input
9.408 MHz clock output
Drum servo reference signal
Discrimination signal determining whether the subcode I/O clock (EXCK) is accepted ("L": accept, "H":
ignore) (Not in use)
Subcode I/O data transfer clock (DUTY50)
Subcode serial data input
Subcode serial data output
Subcode I/O sync signal
Copy data output (Not in use)
Emphasis data output (Not in use)
Mute pin
Mute discrimination signal (''H": muted)
RX PLL lock discrimination signal ("H": locked)
Detects presence or absence of RF ("'H": RF present, "L" during REC)
C1 check result for RF ("H": OK) (Not in use)
Signal for discriminating whether C2 is 1 or 2 times
(C2 — Cl —» C2 or Cl — C2) ("H": 1 time, "L": 2 times) (Not in use)
RF PLL clock output (Not in use)
Test pin (normally "L")
RF signal input
Subcode I/O chip select ("L": select)
RF switching pulse (""L": A-CH, "H": B-CH)
GND
REC data PILOT/PCM discrimination signal (""H": PILOT, during playback: always "L")
Record/playback switching signal ("H": record)
Recording signal output, fixed "L" during playback
Test pin (normally "L")
RX APLL PD output (comparator output)
RX APLL oscillator cell amp input
RX APLL oscillator cell amp inverted output
RX APLL external VCO clock input
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