F4: Rec_Pb Block Diagram - Panasonic DVCPRO50 Service Manual
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F4: REC_PB BLOCK DIAGRAM
P4001
P3002
IC3211<7>
6
14
21A
17B
REC DATA 12
7
13
21B
17C
REC DATA 34
4
16
16B
16B
REC FS
3
20B
16C
REC FS 64
RCV
2
17
19C
16A
REC FS 256
IC3153<4>
P3001
18
2-9
19A
REC_YC[7:0]
DFF
IC3152<4>
(VIN,SDI)
21B
10-13,
TP3150
IC3151<4>1/2
FIFO
106-113
15-18
IN FRM
P3001
IO_VBLK
18C
INCOM HD
WE,RE,
FPGA
18B
INCOM FRM
WRST,
97-104
(PLD)
RRST
18A
INCOM CF
IC3150<4>
P3002
P3002
9
11
INCOM HD
68
28A
28A
REF HD
6
14
INCOM FRM
71
27C
27C
REF FRM
5
15
INCOM CF
72
P3007
P3002
BUFF
4
16
REF HD
73
27B
REF CF
27B
3
17
REF FRM
74
2
18
REF CF
77
P3001
P3002
8
12
SYNC HD
69
16A
24C
SYNC HD
P3002
IC3154<4>
4
16
DIF CF
84
23C
DIF CF
SLICER
3
17
DIF FRM
85
19B
DIF FRM
2
18
DIF HS
87
24A
DIF HS
P3002
P3002
BUFF
11
9
67
PB FRM
28B
28B
PB FRM
12
8
66
PB FRM2
28C
28C
PB FRM2
13
7
65
EE CF
6A
25B
EE CF
14
6
63
EE FRM
6B
25C
EE FRM
15
5
62
V_lock
EE HD
6C
26A
EE HD
27MPLL
P3001
P3001
IC3060<3>
A_IN_N
2
1
21C
22A
INCOM_CLK27
IC3061<3>
134
SEL
4
2
18
H_lock
P3000
P3001
BUFF
3
131
27MPLL
21C
21C
SDI_CLK27
IC3064<3>
12
P3002
P3002
121 119
18
2
7A
25A
EE CLK 27
BUFF
IC3061<3>
P3002
P3002
11
9
27A
27A
REF_CLK_27RP
BUFF
IP3016<2>
P3010
IC3013<2>
2
TDO
6
13
3
TDI
TDI
4
16
25
6
TMS
TMS
5
15
32
8
TCK
TCK
2
18
28
IC3014<2>
P3001
TDO
2
18
6A
ISP TDI
ROM for
4
16
6B
ISP TMS
DV_PROC &
6
14
6C
ISP TCK
IO_VBLK_FPGA
P3001
8
12
IP3017<2>
7A
ISP TDO
13
TDI
P100 P3001
25
TMS
28C
7B
ISP SEL4
32
TCK
P1
P3001
28
9
TDO
7C
7C
CONF INFO
ROM for
CONFIG DONE
RF_PROC_
P3002
P3002
FPGA
29B
29B
8
PB_YC[7:0]
31A
31A
(VOUT)
IC3503<14>
26B,C
26B,C
9
PB DATA 34(AUD_CH34)
8
PB FS2
P4001 P3002
11
7
PB FRM A2
18B
14C
PB DATA 34
12
PB DATA 12(AUD_CH12)
6
18A
14B
PB FS2
13
5
PB FS1
18C
15A
PB FRM A2
BUFFER
14
4
PB FRM A1
17B
13C
PB DATA 12
15
17A
13B
PB FS1
16
17C
14A
PB FRM A1
IC3500<14>
19A
15B
PB FS 256
12
BUFFER
P3002
IC3770<22>
11-14
22B
PB DIF BD 0
4
DIF PB_BD[0-3]
4
6-9
22C
PB DIF BD 1
23A
PB DIF BD 2
BUFF
23B
PB DIF BD 3
5
DIF PB FRP
21C
PB DIF FRP
4
DIF PB SSP
22A
PB DIF SSP
3
DIF REC FRP
19C
REC DIF FRP
2
DIF REC FRP
20A
REC DIF SSP
IC3774<22>
P3002
6-9
4
11-14 4
DIF REC_BD[0-3]
20B
REC DIF BD 0
BUFF
20C
REC DIF BD 1
21A
REC DIF BD 2
21B
REC DIF BD 3
SDTI/1394(OPTION) ONLY
CLK 135 VBLK
CLK 36
22
IC3210<7>
AUD_CH12
13
DIDATA
AUD_CH34
56
DIDATB
12
DILRCKA
55
DILRCKB
REC
31
COMP100
DIBCKA
45
DIBCKB
30
DIMCKA
TP3180
44
REC
DIMCKB
REC FRM
FRM27
IC3180
141
114-121
135-138,
138
15
<5>
156
130-133
178
8
REC
157-164
PREPA[0-7]
REC
8
150,
PREPRO
168-175
REC_PREP_B[0-7]
144-148,
50
141,142
7-14
62
CLK27
REC_IOPR_DATA[0:7]
8
for ADD LINE
153
50,51
REC
CLK18
INT SG
CF
IC3200
IC3201
<6>
[1:0]
<6>
IC3640
DRAM
DRAM
<18>
117
FIFO
REC SHUF MEM
8
CNT
8
41-48
CLK135
120-127
170
VDAT
27
IC3065<3>
REC_FRP
5
VDAT
BUFF
VIDEO
REC_INH
FPS
DATA
REC_INV
11
GEN
VTC,CC
117 COMP V
2-7,
27MHz PLL
9,11
116 SIG V
(V LOCK)
PC
PB_FRP
IC3053,54<3>
FPGA_IO_PROC (VBLK_SUB)
VDAT
PB_HD
IC3752<21>
PB_VBLK
12-19
DEF
IC3750-51
11
PC
<21>
IC3753<21>
8
12-19
FIFO
DEF
32
11
PBFRM 27
132,133,
PB_PREP
82,83
CLK27
DATA[0-7]
IC3550
15
7-14
62
PB_PREP
<15>
IC3501<14>
157-164
A[0-7]
114-121
PB
2,7,
PREPRO
PB
10,31
50
PREP
130-133,
CLK 36
CLK 18
168-175
B[0-7]
135-138
OUT
OUT
COMP100
87
141
22
CLK36
CLK36
IC3600
IC3601
CLK18
<16>
<16>
2,7,
DRAM
DRAM
10,31
PB SHUF MEM
IC3500<14>
IC3055<3>
FS
4,5,
PRO DV
13
14
46
VCO
39,40
SEL
46,47
41
12
FS256
18,26
62
63
49
38
39
7
14
CLK18
24
TP3886
TP3905
PB FRAME A
DV_PWMO
<<Original>>
<<PLAYBACK Signal>>
89
TP3212
REC
REC SSP
COMP
87
FRP
IC3260<9>
49 48
TP3211
13
DV_
107
IC3240
REC FRP
41
40
12
<8>
106
61-63,
PROC_
65
79-82
16
157,158
FPGA
42,43,
(PLD)
83-86
66-69
2-5
45,46
REC
REC
24
VBLK
6-7,
DVBUS
ADD LINE
CLK18
47-50
9-11
CNT
TELETEXT
144-147
117
148,
120-127
150-152
46,47
AVuCOM
AVbus
IF
41
FL3700
20
18
7
PB VBLK
LPF
IC3706
19
ADD LINE
1-5,7-9
TELETEXT
A/D
42,43
47-50
45,46
WE,RE,
WRST,
RRST
FIFO
CNT
196-204
33-38
18-21
13-15,
54-61
40,41
17
8
TP3511
PB FRP
PB
COMP
BD_A
79-82
[0:3]
33-36
110-113
PB_COMP
37,38,
83-86
BD_B[0:3]
40,41
PB
116,117,
PB
119,121
DVBUS
PB_COMP
CNT
32
89
SSP
137,138
TP3512
PB SSP
PB_COMP
30
87
FRP
60-63
58
59
50
51
141
54-57
142
132,133,82,83
PB FRM A
<<REC & EE Signal>>
IC3350<12>
REC_ON_N
170
171
EE_ON_N
REC_ECC_FRP,SSP
62,63
RF_PROC_
FE_CTRL A/B
58-61
FPGA (PLD)
REC_CTRL A/B
54-57
205,
TP3323
206 172
TSR
47
REC
REC
ECC_BD_A
65
53,54
RF CNT
227
48
57,58
REC
27
51
143 HSE_A
ECC
BD_B
59,
61-63
50
144 HSE_B
REC
ECC100
171 RP_L_HSW
170
RP_DATA_A
40
18
168
RP_CLK_A
41
CLK 18
IC3300<11>
IC3290-93
IC3301
<10>
<11>
4
5
6
FIFO
SDRAM
7
DVuCOM
DVuCOM bus
2
IF
3
IC3450<13>
EE_DLY
BD
148,149
214,215
A[0-3]
157,158
161-164
217,218
TRP[0-3]
PB
RF CNT
EE_DLY
PB
BD
150,152
168
CLK_A
15
159,160
B[0-3]
PB
170
DATA_A
14
PB_ECC
53,54
BD_A[3:0]
57,58
PB
RP/PB
171
ECC100
L_HSW
69
PB_ECC
59,
PB
BD_B[3:0]
61-63
175
CLK_B
12
PB
177
PB
DATA_B
205,
11
ECC FRP,SSP
206
RP/PB
178
R_HSW
70
CLK 18
111
SLOW
CNT
SDRAM
SDRAM
112,
113
DVuCOM bus
190
82,83,
132,133
DATA & CLK
191
192
IC3841
134,
128
REC_ECC
129
FRP
DVuP
131
90
IC3050,3051<3>
IC3063<3>
27MHz
2
H WND
PLL
(H LOCK)
3
H ERR
X3050
P3002 P700
6
14
FPS1
4B
11C
7
13
FPS0
4A
11B
9
11
REC_SPA
5A
12C
12
TSR
7B
15A
8
15
TSR_PLD
BUFF
TRP0
5C
13B
16
TRP1
6A
13C
17
2-5
TRP_PLD[0-3]
TRP2
6B
14A
18
TRP3
6C
14B
IC3351<12>
P3001
P5901
15
REC_L_DATA_P
8C
8C
2
16
REC_L_DATA_N
8B
8B
14
REC_R_DATA_P
9B
9B
3
TTL/
13
ECL
REC_R_DATA_N
9C
9C
11
REC_CLK_P
9A
9A
REC_CLK
6
12
REC_CLK_N
8A
8A
IC3381<22>
P3001
P5901
1
RP_L_CLK
15
RP_L_CLK_N
11A
11A
44
2
RP_L_CLK_P
10A
10A
3
45
RP_L_DATA
14
RP_L_DAT_P
10B
10B
4
ECL/
RP_L_DAT_N
10C
10C
5
RP_R_CLK
TTL
37
11
RP_R_CLK_N
12C
12C
6
RP_R_CLK_P
12B
12B
7
RP_R_DATA
RP_R_DAT_P
11C
11C
38
10
8
RP_R_DAT_N
11B
11B
IC3773<22>
P3001
P5901
FE_CTRL_0
9
11
RE CTRL 0
15C
21A
FE_CTRL_1
8
12
RE CTRL 1
16A
21B
FE_CTRL_2
7
13
RE CTRL 2
16B
22A
FE_CTRL_3
6
14
RE CTRL 3
16C
22B
REC_CTRL_A01
5
15
RE CTRL L
17A
23A
4
16
REC_CTRL_B01
RE CTRL R
17B
23B
BUFF
IC3380<22>
P3001
P5901
1
PB_L_CLK
18
15
PB_L_CLK_N
13B
13B
2
PB_L_CLK_P
13C
13C
3
19
PB_L_DATA
14
PB_L_DAT_P
12A
12A
4
ECL/
PB_L_DAT_N
13A
13A
5
TTL
21
PB_R_CLK
11
PB_R_CLK_N
15A
15A
6
PB_R_CLK_P
14A
14A
7
PB_R_DATA
22
10
PB_R_DAT_P
14B
14B
8
PB_R_DAT_N
14C
14C
IC3352<12>
P3002
204
15
5
PBR_HSW
3A
205
16
4
PBL_HSW
2C
206
17
3
RPR_HSW
2B
P3002
207
18
2
RPL_HSW
2A
P3002
P700
200
11
9
TAPE REV P
8A
16B
201
12
8
CUE REV P
5B
13A
202
13
7
FLUSH
3B
10C
203
14
6
SLOW P
4C
12B
BUFF
IC3771<22>
P3002
P700
2
18
FEND
3C
11A
P3002
7
13
SYS_FEND
11C
BUFF
P3002
P4001
3
17
APROC_FEND
18B
22A
4
16
PB_FRM_18
15C 19B
P3002
9
11
SYS_FRP
11A
P3002
8
12
SYS_SSP
11B
IC3064<3>
4
11
9
BUFF
APROC CLK27
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