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Video signal processing (output mode)
Video signal processing is performed for each different system to enable 4K processing and HD processing at the same
time.
Signals multiplexed sequentially with audio data, video data, and uncompressed meta data are transferred through DMA
(Direct Memory Access) from the BANK FPGA (IC1) on the DM-154 board with 3.125 Gbps serial transmission. This
DMA transfer system is independent for 4K signal and HD signal.
Signals transferred from the DM-154 board through DMA are input to the backplane FPGA (IC200) and are stored in
the DRAM (IC3002, IC3003).
The XAVC-I signal separated in the backplane FPGA (IC200) is processed by the video decoder (IC1000, IC1200,
IC1400, IC1600) and the processed signal is input to the baseband FPGA (IC100).
Parallel baseband signals are encoded into the SDI signals in IC100 and the encoded signals are output as SDI signals
from the connectors CN201 to CN204 through the SDI drivers (IC201 to IC208).
Audio signal processing (output mode)
The DIO-95 board has four AES/EBU connectors allowing output for eight channels. Furthermore, the HD SDI
embedded audio signals for 16 channels can be output, and each channel is independently selectable.
Signals multiplexed in the same way as video signals are input to the backplane FPGA (IC200). After the signals are
stored in the DRAM (IC3002, IC3003), only audio signals are separated and sent to the audio FPGA (IC300). IC300
performs processing such as channel selection and gain control. AES/EBU-format digital audio signals are output from
the AES/EBU connectors (CN3601, CN3602).
Timecode signal processing (output mode)
The timecode signal written to the baseband FPGA (IC100) by the CPU is processed for serialization, and is then output
from the timecode output connector (CN302).
1-4-5.
HP-160A Board
The HP-160A board mounted at the front of the unit has the following functions.
• SW-1628 board and LED-528 board LED control
• SW-1628 board switch control
• Power shutdown processing
1-4-6.
DM-154 Board
The DM-154 board has the following main functions.
• BANK memory function (main cache for audio/video data)
• Audio/video reference circuit
• 9-pin remote connector
BANK memory function
The BANK FPGA (IC1) has eighteen pieces of 1 Gbit DRAM chips configuring a 2 Gbyte memory space with the ECC
function. The BANK FPGA functions as an audio/video data cache of the unit.
The DIO-95 board is connected to the SY-422A board with the 3.125 Gbps high-speed serial communication.
Audio/video reference circuit
This circuit has a function to lock the reference signal from the reference input connector (CN1901) and the reference
signal input to the DIO-95 board and send these reference signals to each board.
IC1904 sends a 27 MHz clock signal for the video system and IC1905 sends a 24.576 MHz clock signal for the audio
system to each board.
PWS-4400
1-26
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