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Panasonic MN662785TBUC Manual page 54

Signal processing ic for cds

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MN 6 6 2 7 8 5 T B U C
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
( L ) S T A T p i n c o n t r o l
D a t a ( D 1 5 t o D 0 )
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X 0 0 X
X X X X X X X X X X X X X 0 1 X
X X X X X X X X X X X X X 1 0 X
X X X X X X X X X X X X X 1 1 X
X X X X X X X X X X X X X X X 0
X X X X X X X X X X X X X X X 1
X X X X X X X X X X X X X X X X
M D A T A
M C L K
MLD
 
 
 
 
 
 
 
 
 
 
 
 
 
S T A T o u t p u t  
C o m m a n d
( H E X )
( B 7 t o B 0 )
7 0
7 1
7 2
7 3
7 4
7 6
7 7
7 9
7 A
7 B
7 5
D 2 D 1
D 0
7 E
D
D
D
0 1 1 1 0 1 0 1
2
1
0
   
T i m i n g c h a r t o f S T A T p i n o u t p u t m o d e s e l e c t i o n b y M C L K
 
S y m b o l
F u n c t i o n (*
STAT pin output selection
*   : CRC
   : RESY
   : CLVS
   : NTTSTOP
   : SQOK
   : BSSEL
   : FCLV
   : SUBQ (SQCK sync) / TXTDAT
   : SUBQ (MCLK sync) / TXTDAT
   : ZDET (Zero data detection)
STAT pin output setting
*STAT pin output:
   0. FLAG6  
   0. SENSE
   0. NFLOCK
   0. NTLOCK
  STAT pin output mode selection by MCLK
(excluding the setting of SENSE(01))
   1. FLAG6
   2. SENSE
   3. NFLOCK
   4. NTLOCK
   5. SQOK
   6. CRC
   7. CLVS
   8. NTTSTOP
Clearing FLAG6 output from STAT pin
   *Disabled
    Enabled (Reset of FLAG6)
   
Disc rotation speed data output from STAT pin
   (8-bit data)
 0
 1  2  3  4  5  6  7  8
SDD00026AEM
 T a b l e 7 - 1 - 5 ( 1 2 )
: S e t t i n g a t r e s e t )
5 4

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