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TOSHIBA
TMP90C840
3.2.4
Reset
Xl
eLK
RESET
A¢ - 15
A16 - 19
RD
WR
D¢ - 7
The basic timing of the reset operation is indicated in Fig. 3.2 (5).
In order to reset the TMP90C840, the RESET input must be maintained at
the "0" level for at least ten system clock cycles 00 states).
When
a reset req uest is accepted, all I/O ports (Port 0/
da
ta bu.s DO to 07,
Port l/address bus AO to A7, Port 2/address bus A8 to A15, Port 6 and
Port
n
function as input ports (high impedance state).
The RD, WR
and
CLK
pins that always
function as output ports turn to the "1"
level, and the other input ports (P32, P33, Port 4/address bus A16 to
A19 and P83) turn to the "0" level.
The dedicated input ports remain
unchanged.
The registers and external memory of the CPU also remain
unchanged.
Note, however, that the program counter PC, the interrupt
enable flag IFF and the bank registers BX and BY are cleared to "0".
Register A shows an undefined status.
When the reset is cleared, the CPU starts executing instructions from
the address OOOOH.
"' "
Jl ...Jl Jl Jl Jl ...Jl ...Jl
~
I
\
I
\
-~
{undefined I}---
-
-K
-
~Undef ined \
~
/
~
j
) - - -
~--
- - -
Fig. 3.2 (5)
Reset Timing
MPU90-27
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