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TOSHIBA
TMP90C840
The TMP90C840 CPU has a wait control register (WAITC) that controls
waits by using software.
The configuration of this register is shown
in Fig. 3.2 (2).
P3CR
(FFC7H)
7
6
WAITC
I
0
0
0
1
1
0
1
1
5
4
RDE
ODE
2-state wait
Normal wait
No wait
Reserved
3
2
TXDC
I
1
0
RXDC
I
See "3.5.4 Port 3".
Fig. 3.2 (2)
Wait Control Register
This register is assigned to the bits 6 and 7 of the memory address
FFC7H in the internal I/O register area (the other bits are used for
controlling other
functions).
It
is
reset. to
"00",
whereby the
register is placed in the 2-state wait mode.
In the "2-state wait mode", only the first wait in a bus cycle is
sampled, and all subsequent waits are ignored.
In the "normal wait mode", all wait requests are sampled.
The "no
wait mode" ignores all waits.
3.2.2
Dummy cycles
The timing of dummy cycles is shown in Fig. 3.2 (3).
All through the
dummy cycles, the level of both the RD andWR signals remains at "1"
and wait requests are ignored, with the address bus being undefined.
A dummy cycle is also called an "internal operating cycle".
The bus
cycle becomes the dummy cycle when the CPU reads or write the data
from/to the internal memory or internal I/O area.
Xl
eLK
At/; - 19
~'--~_"""_-+-_-I\_
RD
WR
D¢ - 7
WAIT
Fig. 3.2 (3)
Timing of Dummy Cycles
MPU90-25
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