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Preliminary Spec. ver
1.4
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
FREQUENCY SYNTHESIZER
The frequency synthesizer generates all of the clocks required by the chip. A 25MHz parallel resonant crystal is
connected to the on-chip oscillator. This reference frequency drives an on-chip frequency synthesis PLL that
multiplies the 25MHz clock by five to generate a 125MHz clock.
Also this block generates the 2.5MHz, 5.0MHz, and 10MHz clocks for 10Mbit/s.The clock synthesizer generates all
of the clocks required by the netlist. This reference frequency drives an on-chip frequency clock synthesizer that
generates 20MHz clock phases used in the analog and digital sections of the PHY.
CRYSTAL OSCILLATOR
An on-chip Pierce oscillator generates the transmit frequency reference. The recommended connection of the
crystal to the oscillator circuit is shown in Figure 6-3. A 25 MHz ±50ppm fundamental mode parallel resonant
crystal should be used. The values of the loading capacitors should be adjusted to match the recommended
loading for the crystal used. The recommended crystal is loaded with 15pF capacitors as shown in Figure 6-3.
The external crystal and loading capacitors are connected between the XTAL_IN and XTAL_OUT pins of KS8910 .
Transmit PLL
The frequency synthesis PLL generates a 125 MHz clock from the 25 MHz frequency reference. The PLL uses a
phase-frequency detector, a charge pump, and an voltage controlled oscillator (VCO).
A differential loop filter is integrated on chip. This loop filter forms a second-order loop. Higher order high frequency
filtering is performed on-chip. The VCO gain is 100 MHz/Volt, and the charge pump current is 20 uA. The
recommended components result in a loop bandwidth of 250 KHz and a phase margin of 75 degrees.
XTAL_IN
PIn 15
15pF
GND
Figure 6-3. Crystal Oscillator Connection
100BASE-TX ANALOG BLOCKS
KS8910
Chip
Board
XTAL_OUT
Pin14
15pF
GND
6-3
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