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3.2.2
System Control Register (SYSCR)
Bit
:
MACS
Initial value
:
R/W
R/W
:
SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation
for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI,
enables or disenables MRES pin input, and enables or disenables on-chip RAM.
SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. MACS, INTM1,
INTM0, NMIEG, and RAME bits are initialized in manual reset mode, but the MRESE bit is not
initialized. SYSCR is not initialized in software standby mode.
Bit 7—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the
MAC instruction.
Bit 7
MACS
Description
0
Non-saturating calculation for MAC instruction
1
Saturating calculation for MAC instruction
Bit 6—Reserved: This bit always read as 0 and cannot be modified.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5
Bit 4
INTM1
INTM0
0
0
1
1
0
1
7
6
—
INTM1
0
0
—
R/W
Interrupt
Control Mode
0
—
2
—
5
4
INTM0
NMIEG
0
0
R/W
R/W
Description
Control of interrupts by I bit
Setting prohibited
Control of interrupts by I2 to I0 bits and IPR
Setting prohibited
3
2
MRESE
0
0
R/W
1
0
—
RAME
0
1
—
R/W
(Initial value)
(Initial value)
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