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ø
CS5 to CS2
(RAS)
CAS, LCAS
ø
t
BRQS
BREQ
BACK
A23 to A0
CS7 to CS0,
AS, RD,
HWR, LWR
ø
BREQO
Figure 25-15 External Bus Request Output Timing
TR
TR
p
r
t
CSR
t
CASD1
Figure 25-13 DRAM Self-Refresh Timing
t
BZD
Figure 25-14 External Bus Release Timing
t
BRQOD
TR
C
t
CSD2
t
BRQS
t
BACD
TR
C
t
CSD2
t
CASD1
t
BACD
t
BRQOD
t
BZD
901
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