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Philips Semiconductors
1.3GHz low voltage fractional-N synthesizer
Serial programming bus
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 8
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the
Serial bus timing characteristics. See Figure 8.
V
= V
=+3.0V; T
= +25 C unless otherwise specified.
DD
DDCP
amb
SYMBOL
Serial programming clock; CLK
t
Input rise time
r
t
Input fall time
f
T
Clock period
cy
Enable programming; STROBE
t
Delay to rising clock edge
START
t
Minimum inactive pulse width
W
t
Enable set-up time to next clock edge
SU;E
Register serial input data; DATA
t
Input data to clock set-up time
SU;DAT
t
Input data to clock hold time
HD;DAT
Application information
CLK
DATA
STROBE
1999 Nov 04
PARAMETER
t
t
SU;DAT
HD;DAT
T
cy
ADDRESS
MSB
t
START
Figure 8. Serial Bus Timing Diagram
11
data is latched into different working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
sent: C, B, and A. Table 1 shows the format and the contents of
each word. The D word is normally used for testing purposes. When
sending the B-word, data bits FC7–0 for the fractional compensation
DAC are not loaded immediately. Instead they are stored in
temporary registers. Only when the A-word is loaded, these
temporary registers are loaded together with the main divider ratio.
MIN.
TYP.
–
10
–
10
100
–
40
–
1/f
–
COMP
20
–
20
–
20
–
t
t
r
f
LSB
Product specification
SA7016
MAX.
UNIT
40
ns
40
ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
t
SU;E
t
w
SR01417
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