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Table 1-4 On-chip Peripheral Memory Map (Continued)
Address
X:$FFF6
EMI Write Offset Register (EWOR)
X:$FFF5
Reserved
X:$FFF4
Reserved
X:$FFF3
SHI Receive FIFO/Transmit Register (HRX/HTX)
X:$FFF2
SHI I
X:$FFF1
SHI Host Control/Status Register (HCSR)
X:$FFF0
SHI Host Clock Control Register (HCKR)
X:$FFEF
EMI Refresh Control Register (ERCR)
X:$FFEE
EMI Data Register 1 (EDRR1/EDWR1)
X:$FFED
EMI Offset Register 1 (EOR1)
X:$FFEC
EMI Base Address Register 1 (EBAR1)
X:$FFEB
EMI Control/Status Register (ECSR)
X:$FFEA
EMI Data Register 0 (EDRR0/EDWR0)
X:$FFE9
EMI Offset Register 0 (EOR0)
X:$FFE8
EMI Base Address Register 0 (EBAR0)
X:$FFE7
SAI TX2 Data Register (TX2)
X:$FFE6
SAI TX1 Data Register (TX1)
X:$FFE5
SAI TX0 Data Register (TX0)
X:$FFE4
SAI TX Control/status Register (TCS)
X:$FFE3
SAI RX1 Data Register (RX1)
X:$FFE2
SAI RX0 Data Register (RX0)
X:$FFE1
SAI RX Control/Status Register (RCS)
X:$FFE0
SAI Baud Rate Control Register (BRC)
X:$FFDF
Reserved
:
:
X:$FFC0
Reserved
The EMI, SHI, and SAI also have several dedicated interrupt vector addresses and
control bits to enable and disable interrupts (see Table 1-2 on page 1-13). These
interrupt vectors minimize the overhead associated with servicing an interrupt by
immediately executing the appropriate service routine. Each interrupt can be
programmed to one of three maskable priority levels.
MOTOROLA
2
C Slave Address Register (HSAR)
DSP56009 User's Manual
DSP56009 Architectural Overview
Register
Overview
1-17
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