Circuit Diagram - LG KE820 Service Manual
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7. CIRCUIT DIAGRAM
1
2
3
BASE BAND PROCESSOR
A
1V5_CORE
1V5_CORE
C109
C110
C111
C112
C113
C114
1u
0.1u
0.01u
1u
0.1u
0.01u
VSUPPLY
B
VCXO_EN
R105
R106
R108
NA
22K
390K
U17
BATT_TEMP
M0
W17
RF_TEMP
M1
W16
JACK_TYPE
M2
W15
M7
M
V16
M8
V17
I_MONITOR
M9
W18
REMOTE_ADC
M10
R109
R110
L12
PAOUT1A
3300
100K
M11
PAOUT1B
K12
BB
PAOUT2A
J12
PA_LEVEL
PAOUT2B
C
N15
QX
BB_QX
P15
Q
BB_Q
R13
BB
I
BB_I
R14
IX
BB_IX
B17
TXON_PA
T_OUT0
B16
VIBRATOR_EN
T_OUT1
B15
PA_BAND
T_OUT2
D13
ANT_SW1
T_OUT3
B14
ANT_SW2
T_OUT4
C18
ANT_SW3
T_OUT5
D15
DIGC1~2
MODE
T_OUT6
D14
KP_OUT(4)
T_OUT7
A18
AU_PWR_EN
T_OUT8
C14
LCD_BACKLIGHT
T_OUT9
A16
JACK_DETECT
T_OUT10
C13
_FM_RESET
T_OUT11
D17
AF_PWR_EN
T_OUT12
C15
AFC
AFC
D
C17
RF_EN
RF_STR0
A17
TF_DETECT
RF_STR1
DIGC1~2
B18
RF_CLK
RF_CLK
C16
RF_DA
RF_DATA
TP116
H1
CLKOUT0
EBU
U12
26MHZ_MCLK
F26M
PLL
K19
VCXO_EN
VCXO_EN
DIGA
L18
SIM_IO
CC_IO
SIM
J16
SIM_CLK
CC_CLK
M19
SIM_RST
CC_RST
C12
TF_DAT0
MMCI_DAT0
D12
TF_DAT1
MMCI_DAT1
B12
TF_DAT2
MMCI_DAT2
A12
MMC
TF_DAT3
MMCI_DAT3
E12
TF_CMD
MMCI_CMD
E
C11
TF_CLK
MMCI_CLK
B2
SPK_RCV_SEL
IRDA_RX
A2
DIGD
RPWRON
IRDA_TX
U11
USB_DP
USB_DPLUS
V11
USB
USB_DM
USB_DMINUS
E17
TDO
TDO
D19
TDI
TDI
F16
TMS
TMS
DIGC2
E16
TCK
TCK
C19
_TRST
TRST_N
D18
RTCK
RTCK
E14
TRIG_IN
TRIG_IN
DIGC2
B13
MON1
MON1
DIGC1
A14
MON2
MON2
DIGC1
U8
TRACESYNC
TRACESYNC
V8
TRACECLK
TRACECLK
F
T9
PIPESTAT0
PIPESTAT0
U9
PIPESTAT1
PIPESTAT1
W8
PIPESTAT2
PIPESTAT2
TRACEPKT(0)
R9
TRACEPKT0
TRACEPKT(1)
W9
ETM
TRACEPKT1
TRACEPKT(2)
T10
TRACEPKT2
V9
TRACEPKT(3)
TRACEPKT3
TRACEPKT(4)
U10
TRACEPKT4
TRACEPKT(5)
V10
TRACEPKT5
TRACEPKT(6)
R10
TRACEPKT6
T11
TRACEPKT(7)
TRACEPKT7
DIGD
TRACEPKT(0:7)
G
UART1
3G
2.5G
1
GND
GND
2
RX
RX
RXD_0
3
TX
TX
TXD_0
4
UFLS
NC1
5
RPWRON_EN
ON_SW
ON_SW
6
VBAT
VBAT
VSUPPLY
H
7
PWR
NC2
8
URXD
NC3
9
UTXD
NC4
10
DSR
DSR
11
RTS
RTS_0
12
CTS
CTS_0
1
2
3
4
5
6
1V5_DSP
1V8_MEM
1V8_MEM
2V72_IO
1V8_MEM
2V72_IO
2V85_CARD
2V85_SIM
2V11_RTC
R101
R102
0
C101
C102
C103
0
R104
C104
C105
0.1u
0.1u
0.1u
NA
C115
C116
C117
C118
C119
C120
C121
C122
C123
C124
0.1u
0.1u
0.1u
1u
0.1u
0.01u
1u
0.1u
0.01u
0.1u
0.1u
0.1u
U102
PMB8876
DIGB
DIGA
DIGD
DIGD
VBR
R136
R137
4
5
6
7
8
9
1V5_DSP
3V1_USB
INTEL Memory(512NOR+128SDRAM, 1.8 I/O)
R103
4.7
C106
C107
C108
0.1u
0.1u
0.1u
A(0:24)
H2
TP101
A(0)
EBU_A0
H3
A(1)
EBU_A1
A(2)
J4
EBU_A2
J2
A(3)
EBU_A3
J3
A(4)
EBU_A4
K1
A(5)
EBU_A5
A(6)
K2
EBU_A6
K3
A(7)
EBU_A7
K5
A(8)
EBU_A8
L2
A(9)
EBU_A9
L1
A(10)
EBU_A10
M1
A(11)
EBU_A11
N1
A(12)
EBU_A12
K4
A(13)
EBU_A13
L4
A(14)
EBU_A14
P1
A(15)
EBU_A15
L3
A(16)
EBU_A16
R1
A(17)
EBU_A17
N2
A(18)
EBU_A18
N4
A(19)
EBU_A19
N5
A(20)
EBU_A20
T1
A(21)
EBU_A21
R2
A(22)
EBU_A22
U2
A(23)
EBU_A23
A(24)
V2
EBU_A24
D(0:15)
V4
TP106
D(0)
EBU_AD0
R4
D(1)
EBU_AD1
W3
D(2)
EBU_AD2
T5
D(3)
EBU_AD3
R6
D(4)
EBU_AD4
U5
D(5)
EBU_AD5
W4
D(6)
EBU_AD6
W5
D(7)
EBU_AD7
U6
D(8)
EBU_AD8
V5
D(9)
EBU_AD9
V6
D(10)
EBU_AD10
D(11)
W6
EBU_AD11
T8
D(12)
EBU_AD12
U7
D(13)
EBU_AD13
V7
D(14)
EBU_AD14
R7
D(15)
EBU_AD15
P4
TP114
EBU_CS0_N
_FLASH1_CS
V1
TP115
1V8_MEM
EBU_CS1_N
_RAM_CS
T2
TP117
EBU_CS2_N
_FLASH2_CS
P3
EBU_CS3_N
_CS3
G2
TP119
FCDP_RB_N
FCDP
R122
T7
EBU_ADV_N
_ADV
N3
3300
EBU_RD_N
_RD
U1
EBU_WR_N
_WR
T6
EBU_WAIT_N
_WAIT
M2
EBU_RAS_N
_RAS
M4
EBU_CAS_N
_CAS
M3
EBU_BC0_N
_BC0
P2
EBU_BC1_N
_BC1
U3
R123
22
EBU_SDCLKO
SDCLKO
U4
EBU_SDCLK1
SDCLKI
R3
R124
22
EBU_BFCLKO
BFCLKO
V3
EBU_BFCLKI
BFCLKI
T3
EBU_CKE
CKE
V12
RTC_OUT
RTC_OUT
U13
RTC
F32K
V13
OSC32K
X101
32.768KHz
U14
RTC
RESET_N
_RESET
2
1
P16
VREFN
L17
C131
220n
C132
C133
VREFP
M16
R126
22K
IREF
15p
15p
M15
VDDBB
L15
VSSBB
U18
VDDVBR_1
R17
2V65_ANA
VDDVBR_2
T17
VSSVBR_1
P17
VSSVBR_2
T15
VDDVBT
R16
VSSVBT
T14
VDDD
U16
VSSD
V14
VDDM
V15
VSSM
K17
VDDBG
DIGD
N19
DIGD
DIGA
VSSBG
N16
C134
C135
C136
AGND
DIGA
DIGD
K15
GUARD
0.1u
0.1u
0.1u
2V72_IO
1K
1K
Changed by:
mentor
7
8
9
- 119 -
10
11
U101
PF38F5060M0Y0B0
A(0:24)
D(0:15)
A(0)
D1
M2
D(0)
A0
DQ0
A(1)
C1
L1
D(1)
A1
DQ1
A(2)
D(2)
B1
K1
A2
DQ2
A(3)
B2
L2
D(3)
A3
DQ3
A(4)
A2
M4
D(4)
A4
DQ4
A(5)
B3
L3
D(5)
A5
DQ5
A(6)
D(6)
A3
L4
A6
DQ6
A(7)
A4
L5
D(7)
A7
DQ7
A(8)
G8
M5
D(8)
A8
DQ8
A(9)
F8
L6
D(9)
A9
DQ9
A(10)
E8
M6
D(10)
A10
DQ10
A(11)
G9
L7
D(11)
A11
DQ11
A(12)
F9
L8
D(12)
A12
DQ12
A(13)
E9
K9
D(13)
A13
DQ13
A(14)
D9
L9
D(14)
A14
DQ14
A(15)
C9
M8
D(15)
A15
DQ15
A(16)
B9
A16
A(17)
B4
D5
TP209
A17
_F_ADV
_ADV
A(18)
B5
G3
A18
_F1_CE
_FLASH1_CS
A(19)
A5
G2
A19
_F2_CE
A(20)
F7
H3
A20
_F3_CE
A(21)
E7
E6
R112
22
A21
_F4_CE_A27
BFCLKI
A(22)
B7
K5
A22
F_CLK
BFCLKO
A(23)
A6
J5
A23
D_CLK
SDCLKO
1V8_MEM
A(24)
A7
H5
A24
_D_CLK
SDCLKI
A8
H7
R113
22
TP105
A25
_OE
_RD
B8
G7
R114
10K
A26
_F_RST
_RESET
J9
F_WAIT
_WAIT
J1
E2
1V8_MEM
TP107
F_VPP
_WE
_WR
H6
_D_WE
C125
C126
D4
E1
R115
NA
F_VCC1
_F_WP1
_WP
D6
F1
R117
0
F_VCC2
_F_WP2
0.1u
0.1u
J4
B6
TP108
F_VCC3
F_DPD
F_DPD
J6
E5
F_VCC4
N_CLE
D8
N_ALE
R118
C5
D_VCC1
D3
H1
100K
D_VCC2
N_RY__BY
D7
D_VCC3
C127
C128
G6
TP109
R445
NA
JP0
D_CKE
CKE
D2
G4
R443
0
JP1
A(12)
S_VCC
D_BA0
0.1u
0.1u
H4
R444
0
JP2
A(13)
D_BA1
J2
F4
TP112
R446
NA
JP3
A(14)
VCCQ1
_D_RAS
_RAS
J3
F3
TP113
VCCQ2
_D_CAS
_CAS
J7
F2
128M SDRAM
256M SDRAM
VCCQ3
_D1_CS
_RAM_CS
J8
E3
JP0
Open
Short
VCCQ4
_D2_CS
H9
JP1
Short
Open
D_DM0__S_LB
_BC0
C129
C130
C2
H8
JP2
Short
Open
VSS1
D_DM1__S_UB
_BC1
C3
M7
JP3
Open
Short
VSS2
D_UDQS
0.1u
0.1u
C4
M3
VSS3
D_LDQS
C6
F6
VSS4
_S_CS1
C7
H2
VSS5
S_CS2
C8
VSS6
K2
VSS7
K3
A1
VSS8
DU1
K4
A9
VSS9
DU2
K6
M1
VSS10
DU3
K7
M9
VSS11
DU4
K8
G1
VSS12
RFU
ON BOARD ARM9 JTAG & ETM INTERFACE
2V72_IO
1V8_MEM
CN101
G1
G2
1
30
TRACEPKT(0:7)
2
29
TRACECLK
3
28
TRACEPKT(7)
4
27
_TRST
TRACEPKT(6)
5
26
TDI
TRACEPKT(5)
6
25
TRACEPKT(4)
TMS
7
24
TRACEPKT(3)
TCK
8
23
RTCK
TRACEPKT(2)
9
22
TDO
TRACEPKT(1)
10
21
TRACEPKT(0)
_EXTRST
11
20
TRIG_IN
PIPESTAT2
12
19
TRIG_OUT
PIPESTAT1
13
18
PIPESTAT0
14
17
TRACESYNC
15
16
G3
G4
TP129
MON1
TP130
MON2
Engineer:
LG Electronics
Drawn by:
T.K.CHOI
R&D CHK:
W.J.KIM
TITLE:
KE820
DOC CTRL CHK:
Issue 1.0
MFG ENGR CHK:
Date Changed:
Time Changed:
QA CHK:
REV:
Drawing Number:
v1.0
2005-10-11
3:07:35 pm
10
11
12
A
B
C
D
E
F
G
H
Size:
A3
12 1 8 A
Page:
1/5
12
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