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Master mode and slave mode can be specified by the external mode pins. Partial-sharing master
mode is entered from master mode by means of a software setting. See Appendix C, Mode Pin
Settings, for the external mode pin settings. In master mode and slave mode, the bus goes to the
high-impedance state when not being held, so that it is possible to directly connect the master
mode and slave mode chips. In partial-sharing master mode, the bus is constantly driven, and
therefore an external buffer is necessary for connection to the master bus. In master mode, it is
possible to connect an external device that issues bus requests instead of a slave mode chip. In the
following description, an external device that issues bus requests is also referred to as a slave.
The SH7750 Series has two internal bus masters: the CPU and the DMAC. When synchronous
DRAM or DRAM is connected and refresh control is performed, refresh requests constitute a third
bus master. In addition to these are bus requests from external devices in master mode. If requests
occur simultaneously, priority is given, in high-to-low order, to a bus request from an external
device, a refresh request, the DMAC, and the CPU.
To prevent incorrect operation of connected devices when the bus is transferred between master
and slave, all bus control signals are negated before the bus is released. When mastership of the
bus is received, also, bus control signals begin driving the bus from the negated state. Since
signals are driven to the same value by the master and slave exchanging the bus, output buffer
collisions can be avoided. By turning off the output buffer on the side releasing the bus, and
turning on the output buffer on the side receiving the bus, simultaneously with respect to the bus
control signals, it is possible to eliminate the signal high-impedance period. It is not necessary to
provide the pull-up resistors usually inserted in these control signal lines to prevent incorrect
operation due to external noise in the high-impedance state.
Bus transfer is executed between bus cycles.
When the bus release request signal (%5(4) is asserted, the SH7750 Series releases the bus as
soon as the currently executing bus cycle ends, and outputs the bus use permission signal (%$&.).
However, bus release is not performed during multiple bus cycles generated because the data bus
width is smaller than the access size (for example, when performing longword access to 8-bit bus
width memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus
release is not performed between read and write cycles during execution of a TAS instruction, or
between read and write cycles when DMAC dual address transfer is executed. When %5(4 is
negated, %$&. is negated and use of the bus is resumed. See Appendix E, Pin Functions, for the
pin states when the bus is released.
When a refresh request is generated, the SH7750 Series performs a refresh operation as soon as
the currently executing bus cycle ends. However, refresh operations are deferred during multiple
bus cycles generated because the data bus width is smaller than the access size (for example, when
performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a
cache fill or write-back, and also between read and write cycles during execution of a TAS
instruction, and between read and write cycles when DMAC dual address transfer is executed.
Refresh operations are also deferred in the bus-released state.
Rev. 4.0, 04/00, page 412 of 850
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