Toshiba TXZ+ TMPM3HNF10BDFG Manuals

Manuals and User Guides for Toshiba TXZ+ TMPM3HNF10BDFG. We have 1 Toshiba TXZ+ TMPM3HNF10BDFG manual available for free PDF download: Reference Manual

Toshiba TXZ+ TMPM3HNF10BDFG Reference Manual (71 pages)

32-bit RISC Microcontroller

Brand: Toshiba | Category: Microcontrollers | Size: 0.99 MB

Table of Contents
2
Contents
2
List of Figures
5
List to Tables
5
Preface
6
Related Documents
6
Conventions
7
Terms and Abbreviations
9
Clock Control and Operation Mode
10
Outlines
10
Clock Control
11
Clock Type
11
The Initial Value by a Reset Operation
11
Clock System Diagram
12
Figure 1.1 Clock System Diagram
12
Warming up Function
13
The Warming up Timer for a High Speed Oscillation
13
The Warming up Timer for a Low Speed Oscillation
14
The Directions for Warming up Timer
14
Clock Multiplying Circuit (PLL) for Fsys
15
A PLL Setup after Reset Release
15
The Formula and the Example of a Setting of a PLL Multiplication Value
15
Change of the PLL Multiplication Value under Operation
17
PLL Operation Start/Stop/Switching Procedure
17
System Clock
18
The Setting Method of a System Clock
19
Clock Supply Setting Function
21
The Output Function of a Clock in the Terminal
21
Prescaler Clock
21
Operation Mode
22
Details of an Operation Mode
22
The Feature in each Mode
22
Low Power Consumption Mode
23
Selection of a Low Power Consumption Mode
23
The Peripheral Function State in a Low Power Consumption Mode
23
Mode State Transition
26
IDLE Mode Transition Flow
26
Figure 1.2 Mode State Transition
26
STOP1 Mode Transition Flow
27
STOP2 Mode Transition Flow
28
The Return Operation from a Low Power Consumption Mode
29
The Release Source of a Low Power Consumption Mode
29
Warming up at the Release of Low Power Consumption Mode
31
The Restart Operation from the STOP2 Mode
32
Figure 1.3 STOP2 Mode Restart Operation Flow
32
Clock Operation by Mode Transition
33
NORMAL → IDLE → NORMAL Operation Mode Transition
33
NORMAL → STOP1 → NORMAL Operation Mode Transition
33
Figure 1.4 NORMAL → STOP1 → NORMAL Operation Mode Transition
33
NORMAL → STOP2 → RESET → NORMAL Operation Mode Transition
34
Figure 1.5 NORMAL → STOP2 → RESET → NORMAL Operation Mode Transition
34
Explanation of Register
35
Register List
35
Clock and Mode Control
35
Low Speed Oscillation/Power Control (Note)
35
Register Description
36
CGPROTECT] (CG Write Protection Register)
36
CGOSCCR] (Oscillation Control Register)
36
CGSYSCR] (System Clock Control Register)
37
CGSTBYCR] (Standby Control Register)
38
CGSCOCR] (SCOUT Output Control Register)
38
CGPLL0SEL] (PLL Selection Register for Fsys)
39
CGWUPHCR] (High Speed Oscillation Warming up Register)
39
CGWUPLCR] (Low Speed Oscillation Warming up Register)
40
CGFSYSMENB] (Clock Supply and Stop Register B for Fsysm)
41
CGFSYSENA] (Clock Supply and Stop Register a for Fsys)
42
CGFSYSENB] (Clock Supply and Stop Register B for Fsys)
44
CGFCEN] (Clock Supply and Stop Register for Fc)
46
CGSPCLKEN] (Clock Supply and Stop Register for ADC and Debug Circuit)
46
RLMLOSCCR] (Low Speed Oscillation Control Register)
46
RLMSHTDNOP] (Power Supply Cut off Control Register)
46
RLMPROTECT] (RLM Write Protection Register)
47
Information According to Product
48
Cgfsysmenb]
48
Cgfsysena]
49
Cgfsysenb]
50
Memory Map
51
Overview
51
Tmpm3Hxf10B
52
Figure 2.1 Tmpm3Hxf10
52
Tmpm3Hxfdb
53
Figure 2.2 Tmpm3Hxfd
53
Bus Matrix
54
Structure
54
Single Chip Mode
54
Figure 2.3 Single Chip Mode
54
Single Boot Mode
55
Figure 2.4 Single Boot Mode
55
Connection Table
56
Code Area/ SRAM Area
56
Peripheral Area
57
Power Supply and Reset Operation
58
Outline
58
Function and Operation
59
Cold Reset
59
Reset by a Power on Reset Circuit (Without Using a RESET_N Pin)
60
Figure 3.1 the Reset Operation by a Power on Reset Circuit
60
Reset by a RESET_N Pin
61
Figure 3.2 Reset Operation by a RESET_N Pin (1)
61
Figure 3.3 Reset Operation by a RESET_N Pin (2)
62
Continuation of Reset by LVD
63
Figure 3.4 Reset Operation by LVD Reset
63
Warm Reset
64
Warm Reset by RESET_N Pin
64
Warm Reset by Internal Reset
64
Figure 3.5 Warm Reset Action
64
Reset by STOP2 Mode Release
65
Starting in Reset and Single Boot Mode
65
Figure 3.6 Starting in Power Supply Is on and Single Boot Mode
65
Figure 3.7 Starting in the Single Boot Mode When Power Supply Is Stable
66
Power on Reset Circuit
67
Operation at the Time of Turn on
67
Operation at the Time of Turn off
67
Figure 3.8 Power on Reset Circuit
67
About Turn on Power Supply after Turn off
68
When Using External Reset Circuit or Internal LVD Reset Output
68
When Not Using External Reset Circuit and Internal LVD Reset Output
68
After Reset Release
68
A Reset Factor and the Reset Initialized Range
69
Revision History
70
Restrictions on Product Use
71

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Toshiba TXZ+ TMPM3HNF10BDFG Reference Manual (71 pages)

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