Motorola MC68HC908GP32 Technical Data Manual

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Freescale Semiconductor, Inc.

MC68HC908GP32

MC68HC08GP32

Technical Data

M68HC08

Microcontrollers

MC68HC908GP32/H

Rev. 6, 8/2002

MOTOROLA.COM/SEMICONDUCTORS

For More Information On This Product,

Go to: www.freescale.com

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Summary of Contents for Motorola MC68HC908GP32

Page 1 Freescale Semiconductor, Inc. MC68HC908GP32 MC68HC08GP32 Technical Data M68HC08 Microcontrollers MC68HC908GP32/H Rev. 6, 8/2002 MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com...
Page 2 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com...
Page 3 Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use...
Page 4 21-2, Timebase control register, bit 0 is a reserved bit. July, 2001 Updated crystal oscillator component values in 23.17.1 CGM Component Specifications. Added appendix A: MC68HC08GP32 — ROM part. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 5 Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 List of Sections Section 1. General Description ....31 Section 2. Memory Map ......43 Section 3.
Page 6 Section 25. Ordering Information ....395 Appendix A. MC68HC08GP32 ....397 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 7: Table Of Contents
Features ......... . 32 1.3.1 Standard Features of the MC68HC908GP32... . 32 1.3.2 Features of the CPU08.
Page 8 Stop Mode ........62 Keyboard Interrupt Module (KBI) ..... . . 62 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 9 Illegal Address Reset ......74 4.3.4 SIM Reset Status Register ......74 MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 10 I/O Signals ........91 Technical Data MC68HC908GP32 MC68HC08GP32 Rev.
Page 11 Features ......... 107 Functional Description ......107 MC68HC908GP32 MC68HC08GP32 Rev.
Page 12 Choosing a Filter ....... . 135 Technical Data MC68HC908GP32 MC68HC08GP32 Rev.
Page 13 Features ......... 148 MC68HC908GP32 MC68HC08GP32 Rev.
Page 14 11.10 Stop Mode ........173 Technical Data MC68HC908GP32 MC68HC08GP32 Rev.
Page 15 Features ......... 189 14.4 Functional Description ......190 MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 16 Port B Data Register ......219 16.4.2 Data Direction Register B ......220 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 17 Receiver ........248 MC68HC908GP32 MC68HC08GP32 Rev.
Page 18 External Pin Reset ....... 283 19.4.2 Active Resets from Internal Sources ....284 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 19 Master Mode ........307 MC68HC908GP32 MC68HC08GP32 Rev.
Page 20 Features ......... 335 Technical Data MC68HC908GP32 MC68HC08GP32 Rev.
Page 21 22.10.1 TIM Status and Control Register ....356 22.10.2 TIM Counter Registers ......358 MC68HC908GP32 MC68HC08GP32 Rev.
Page 22 23.17.2 CGM Electrical Specifications ..... . 388 23.18 Memory Characteristics ......389 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 23 Memory Characteristics ......405 ROM MC Order Numbers ......406 MC68HC908GP32 MC68HC08GP32 Rev.
Page 24: Motorola For More Information On This Product
Freescale Semiconductor, Inc. Table of Contents Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Table of Contents MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 25 Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 List of Figures Figure Title Page MCU Block Diagram ....... . . 36 40-Pin PDIP Pin Assignments .
Page 26 13-4 Keyboard Interrupt Enable Register (INTKBIER) ..188 14-1 LVI Module Block Diagram ......191 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 27 18-5 SCI Receiver Block Diagram ......249 18-6 Receiver Data Sampling ......250 MC68HC908GP32 MC68HC08GP32 Rev.
Page 28 20-2 SPI Module Block Diagram......306 20-3 Full-Duplex Master-Slave Connections ....307 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 29 = 2.7 Vdc) ....374 23-3 Typical High-Side Driver Characteristics – Port PTC4–PTC0 (V = 4.5 Vdc) ....375 MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 30 Typical Stop Mode I ......405 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 31 Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32 List of Tables Table Title Page Vector Addresses ........55 Interrupt Sources .
Page 32 25-1 MC Order Numbers ....... . 395 Summary of MC68HC08GP32 and MC68HC908GP32 differences .
Page 33: Section 1. General Description
Features ......... . 32 1.3.1 Standard Features of the MC68HC908GP32... . 32 1.3.2 Features of the CPU08.
Page 34: Introduction
3.0-V and 5.0-V operation – Illegal opcode detection with reset – Illegal address detection with reset 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data...
Page 35 • Timebase module with clock prescaler circuitry for eight user selectable periodic real-time interrupts with optional active clock source during stop mode for periodic wakeup from stop using an external 32-kHz crystal MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 36: Features Of The Cpu08
40-pin plastic dual-in-line package (PDIP), 42-pin shrink dual-in- line package (SDIP), or 44-pin quad flat pack (QFP) • Specific features of the MC68HC908GP32 in 40-pin PDIP are: – Port C is only 5 bits: PTC0–PTC4 – Port D is only 6 bits: PTD0–PTD5; single 2-channel TIM module •...
Page 37: Figure
MCU Block Diagram 1.4 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908GP32. Text in parentheses within a module block indicates the module name. Text in parentheses next to a signal indicates the module which uses the signal.
Page 38: Motorola For More Information On This Product
Freescale Semiconductor, Inc. General Description Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — General Description MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 39: 40-Pin Pdip Pin Assignments
Internal connection PTC5 Connected to ground PTC6 Connected to ground PTD6/T2CH0 Unconnected PTD7/T2CH1 Unconnected Figure 1-2. 40-Pin PDIP Pin Assignments MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA General Description For More Information On This Product, Go to: www.freescale.com...
Page 40: 42-Pin Sdip Pin Assignments
Pins not available on 42-pin package Internal connection PTC5 Connected to ground PTC6 Connected to ground Figure 1-3. 42-Pin SDIP Pin Assignments Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — General Description MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 41: 44-Pin Qfp Pin Assignments
To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-5 shows. Place the C1 bypass capacitor as close to the MCU as possible. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 42: Power Supply Bypassing
(SIM). 1.6.4 External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Section 12. External Interrupt (IRQ). Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — General Description MOTOROLA For More Information On This Product,...
Page 43: Port A Input/Output (I/O) Pins (Pta7/Kbd7–Pta0/Kbd0)
1.6.9 Port B I/O Pins (PTB7/AD7—PTB0/AD0) PTB7–PTB0 are general-purpose, bidirectional I/O port pins that can also be used for analog-to-digital converter (ADC) inputs. See Section 16. Input/Output (I/O) Ports Section 5. Analog-to-Digital Converter (ADC). MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA General Description For More Information On This Product, Go to: www.freescale.com...
Page 44: Port C I/O Pins (Ptc6–Ptc0)
Any unused inputs and I/O ports should be tied to an appropriate logic level (either V or V ). Although the I/O ports of the MC68HC908GP32 do not require termination, termination is recommended to reduce the possibility of static damage. Technical Data MC68HC908GP32 MC68HC08GP32 Rev.
Page 45: Section 2. Memory Map
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 2. Memory Map 2.1 Contents Introduction ........43 Unimplemented Memory Locations .
Page 46: Reserved Memory Locations
$FFFF; COP control register, COPCTL Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Memory Map MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 47: Memory Map
Break Status and Control Register (BRKSCR) $FE0C LVI Status Register (LVISR) $FE0D Unimplemented ↓ 3 Bytes $FE0F Figure 2-1. Memory Map MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com...
Page 48 $FFDB $FFDC Note: $FFF6–$FFFD FLASH Vectors ↓ reserved for 36 Bytes 8 security bytes $FFFF Figure 2-1. Memory Map (Continued) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Memory Map MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 49: Control, Status, And Data Registers
$0009 Unimplemented Write: Reset: = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Memory Map For More Information On This Product,...
Page 50 Write: (SCC1) Reset: = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Memory Map MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 51 Register Write: (INTSCR) Reset: = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Memory Map For More Information On This Product,...
Page 52 † One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset). = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Memory Map...
Page 53 Write: (T2CH0H) Reset: Indeterminate after reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Memory Map For More Information On This Product,...
Page 54 Write: (PMDS) Reset: = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Memory Map MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 55 $FE05 Write: (INT2) Reset: = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Memory Map For More Information On This Product,...
Page 56 Unaffected by reset † Non-volatile FLASH register = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Memory Map MOTOROLA For More Information On This Product,...
Page 57 IRQ Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — Highest $FFFF Reset Vector (Low) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com...
Page 58: Motorola For More Information On This Product
Freescale Semiconductor, Inc. Memory Map Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Memory Map MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 59: Section 3. Low-Power Modes
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 3. Low-Power Modes 3.1 Contents Introduction ........58 3.2.1...
Page 60: Introduction
CPU clock is disabled but the bus clock continues to run. Power consumption can be further reduced by disabling the LVI module and/or the timebase module through bits in the CONFIG register. (See Section 8. Configuration Register (CONFIG).) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Low-Power Modes...
Page 61: Stop Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the break status register is set. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 62: Stop Mode
The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 63: Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 64: External Interrupt Module (Irq)
3.9.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 65: Stop Mode
SCI register states. SCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 66: Serial Peripheral Interface Module (Spi)
The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 67: Timebase Module (Tbm)
• External reset — A logic 0 on the RST pin resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 68 – $FFF0 and $FFF1; TIM2 channel 0 • Serial peripheral interface module (SPI) interrupt — A CPU interrupt request from the SPI loads the program counter with the contents of: Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Low-Power Modes...
Page 69: Exiting Stop Mode
MCU and loads the program counter tripf with the contents of locations $FFFE and $FFFF. • Break interrupt — A break interrupt loads the program counter with the contents of locations $FFFC and $FFFD. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 70 SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. NOTE: Use the full stop recovery time (SSREC = 0) in applications that use an external crystal. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Low-Power Modes...
Page 71: Section 4. Resets And Interrupts
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 4. Resets and Interrupts 4.1 Contents Introduction ........70 Resets.
Page 72: Introduction
4.3.2 External Reset A logic 0 applied to the RST pin for a time, t , generates an external reset. An external reset sets the PIN bit in the SIM reset status register. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 73: Internal Reset Timing
32 CGMXCLK cycles after releasing the RST pin. PULLED LOW BY MCU RST PIN 32 CYCLES 32 CYCLES CGMXCLK INTERNAL RESET Figure 4-1. Internal Reset Timing MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Resets and Interrupts For More Information On This Product,...
Page 74: Power-On Reset Recovery
CGMXCLK CGMOUT RST PIN INTERNAL RESET 1. PORRST is an internally generated power-on reset pulse. Figure 4-2. Power-On Reset Recovery Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Resets and Interrupts MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 75: Cop Reset
An illegal opcode reset sets the ILOP bit in the SIM reset status register. If the stop enable bit, STOP, in the mask option register is a logic 0, the STOP instruction causes an illegal opcode reset. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 76: Sim Reset Status Register (Srsr)
Figure 4-3. SIM Reset Status Register (SRSR) POR — Power-On Reset Flag 1 = Power-on reset since last read of SRSR 0 = Read of SRSR since last power-on reset Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Resets and Interrupts...
Page 77: Interrupts
An interrupt: • Saves the CPU registers on the stack. At the end of the interrupt, the RTI instruction recovers the CPU registers from the stack so that normal processing can resume. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 78: Interrupt Stacking Order
In the example shown Figure 4-5, if an interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Resets and Interrupts...
Page 79: Interrupt Recognition Example
If the interrupt service routine modifies the H register or uses the indexed addressing mode, save the H register and then restore it prior to exiting the routine. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 80: Interrupt Processing
LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION INSTRUCTION UNSTACK CPU REGISTERS INSTRUCTION EXECUTE INSTRUCTION Figure 4-6. Interrupt Processing Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Resets and Interrupts MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 81: Sources
TBIE IF16 $FFDC–$FFDD Note: 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction. 2. 0 = highest priority MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Resets and Interrupts For More Information On This Product, Go to: www.freescale.com...
Page 82: Swi Instruction
The channel x interrupt enable bit, CHxIE, enables channel x TIM1 CPU interrupt requests. CHxF and CHxIE are in the TIM1 channel x status and control register. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 83: Tim2
MODFEN bit set. The error interrupt enable bit, ERRIE, enables MODF CPU interrupt requests. MODF, MODFEN, and ERRIE are in the SPI status and control register. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 84: Sci
SCI data register. The overrun interrupt enable bit, ORIE, enables OR to generate SCI error CPU interrupt requests. OR is in SCI status register 1. ORIE is in SCI control register 3. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 85: Kbd0-Kbd7 Pins
TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Interrupts must be acknowledged by writing a logic 1 to the TACK bit. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 86: Interrupt Status Registers
SPI transmit IF10 SCI error IF11 SCI receive IF12 SCI transmit IF13 Keyboard IF14 ADC conversion complete IF15 Timebase IF16 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Resets and Interrupts MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 87: Interrupt Status Register 1 (Int1)
IF14–IF7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from the sources shown in Table 4-2. 1 = Interrupt request present 0 = No interrupt request present MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA...
Page 88: Interrupt Status Register 3 (Int3)
Table 4-2. 1 = Interrupt request present 0 = No interrupt request present Bits 7–2 — Always read 0 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Resets and Interrupts MOTOROLA For More Information On This Product,...
Page 89: Section 5. Analog-To-Digital Converter (Adc)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 5. Analog-to-Digital Converter (ADC) 5.1 Contents Introduction ........88 Features .
Page 90: Introduction
When the conversion is completed, ADC places the result in the ADC data register and sets a flag or generates an interrupt. (See Figure 5-1.) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Analog-to-Digital Converter (ADC) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 91: Adc Block Diagram
I/O. Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC will return a logic 0. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 92: Voltage Conversion
ADC data register. In single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs between writes to the ADSCR. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 93: Accuracy And Precision
Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. 5.7 I/O Signals The ADC module has eight pins shared with port B, PTB7/AD7–PTB0/AD0. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 94: Adc Analog Power Pin (Vddad )/ Adc Voltage Reference High Pin (Vrefh )
These I/O registers control and monitor ADC operation: • ADC status and control register (ADSCR) • ADC data register (ADR) • ADC clock register (ADCLK) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Analog-to-Digital Converter (ADC) MOTOROLA For More Information On This Product,...
Page 95: Adc Status And Control Register (Adscr)
ADR register at the end of each conversion. Only one conversion is completed between writes to the ADSCR when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 96 Reserved REFH REFL ADC power off NOTE: If any unused channels are selected, the resulting ADC conversion will be unknown or reserved. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Analog-to-Digital Converter (ADC) MOTOROLA For More Information On This Product,...
Page 97: Adc Data Register (Adr)
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 5-2 shows the available clock configurations. The ADC clock should be set to approximately 1 MHz. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 98 1 = Internal bus clock 0 = External clock (CGMXCLK) ADC input clock frequency ----------------------------------------------------------------------- 1MHz ADIV2 ADIV0 – Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Analog-to-Digital Converter (ADC) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 99: Introduction
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 6. Break Module (BRK) 6.1 Contents Introduction ........97 Features .
Page 100: Features
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 6-1 shows the structure of the break module. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Break Module (BRK)
Page 101: Break Module Block Diagram
$FE0B Register Write: (BRKSCR) Reset: = Unimplemented = Reserved Note: Writing a logic 0 clears SBSW. Figure 6-2. I/O Register Summary MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Break Module (BRK) For More Information On This Product, Go to: www.freescale.com...
Page 102: Flag Protection During Break Interrupts
SBSW is set. See Section 3. Low-Power Modes. Clear the SBSW bit by writing logic 0 to it. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Break Module (BRK)
Page 103: Break Status And Control Register (Brkscr)
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 104: Break Address Register High (Brkh)
$FE0A Bit 7 Bit 0 Read: Bit 7 Bit 0 Write: Reset: Figure 6-5. Break Address Register Low (BRKL) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Break Module (BRK) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 105: Sim Break Status Register (Sbsr)
; then just decrement low byte. HIBYTE,SP ; Else deal with high byte also. DOLO LOBYTE,SP ; Point to WAIT/STOP opcode. RETURN PULH ; Restore H register. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Break Module (BRK) For More Information On This Product,...
Page 106: Sim Break Flag Control Register (Sbfcr)
MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 107: Section 7. Clock Generator Module (Cgmc)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 7. Clock Generator Module (CGMC) 7.1 Contents Introduction ........106 Features .
Page 108: Introduction
CGMOUT/2. In monitor mode, PTC3 determines the bus clock. The PLL is a fully functional frequency generator designed for use with crystals or ceramic resonators. The PLL can generate an 8-MHz bus frequency using a 32-kHz crystal. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 109: Features
CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 7-1 shows the structure of the CGMC. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 110: Cgmc Block Diagram
(TO SIM) CONTROL LOCK AUTO PLLIE PLLF MUL11–MUL0 PRE1–PRE0 CGMVDV FREQUENCY FREQUENCY DIVIDER DIVIDER Figure 7-1. CGMC Block Diagram Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Clock Generator Module (CGMC) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 111: Crystal Oscillator Circuit
Reference divider • Frequency prescaler • Modulo VCO frequency divider • Phase detector • Loop filter • Lock detector MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Clock Generator Module (CGMC) For More Information On This Product, Go to: www.freescale.com...
Page 112 . The circuit determines the mode of the PLL and the lock condition based on this comparison. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Clock Generator Module (CGMC)
Page 113: Acquisition And Tracking Modes
LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. (See 7.7 Interrupts for information and precautions on using interrupts.) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 114 The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below BUSMAX Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 115: Programming The Pll
The relationship between the VCO frequency, f , and the VCLK reference frequency, f , is RCLK ----------- f VCLK RCLK MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Clock Generator Module (CGMC) For More Information On This Product,...
Page 116 N max Then recalculate N: ×   VCLKDES   round ------------------------------------ -   × RCLK Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Clock Generator Module (CGMC) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 117 , and f must be as close as VCLKDES possible to f VCLK NOTE: Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Clock Generator Module (CGMC) For More Information On This Product, Go to: www.freescale.com...
Page 118 32.768 kHz 4.9152 MHz 32.768 kHz 5.0 MHz 32.768 kHz 7.3728 MHz 32.768 kHz 8.0 MHz 32.768 kHz Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Clock Generator Module (CGMC) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 119: Special Programming Exceptions
0. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 120: Cgmc External Connections
Filter network Routing should be done with great care to minimize signal cross talk and noise. 23.17.1 CGM Component Specifications for capacitor and resistor values. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Clock Generator Module (CGMC) MOTOROLA For More Information On This Product,...
Page 121: I/O Signals
7.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 7.5.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 122: External Filter Capacitor Pin (Cgmxfc)
If this bit is set, the Oscillator continues running during stop mode. If this bit is not set (default), the oscillator is controlled by the SIMOSCEN signal which will disable the oscillator during stop mode. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 123: Crystal Output Frequency Signal (Cgmxclk)
(See 7.6.3 PLL Multiplier Select Register High.) • PLL multiplier select register low (PMSL) (See 7.6.4 PLL Multiplier Select Register Low.) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Clock Generator Module (CGMC) For More Information On This Product,...
Page 124: Cgmc I/O Register Summary
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. Figure 7-3. CGMC I/O Register Summary Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 125: Pll Control Register
1 = Change in lock condition 0 = No change in lock condition NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 126 PLL.) PRE1 and PRE0 cannot be written when the PLLON bit is set. Reset clears these bits. NOTE: The value of P is normally 0 when using a 32.768-kHz crystal as the reference. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Clock Generator Module (CGMC)
Page 127: Pll Bandwidth Control Register
Indicates when the PLL is locked • In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode • In manual operation, forces the PLL into acquisition or tracking mode MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA...
Page 128: Pll Bandwidth Control Register (Pbwc)
Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Clock Generator Module (CGMC)
Page 129: Pll Multiplier Select Register High
The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). Bit7–Bit4 — Unimplemented Bits These bits have no function and always read as logic 0s. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 130: Pll Multiplier Select Register Low
$0001. Reset initializes the register to $40 for a default multiply value of 64. NOTE: The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Clock Generator Module (CGMC)
Page 131: Pll Vco Range Select Register
(BCS = 1) if the VCO range select bits are all clear. The PLL VCO range select register must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 132: Pll Reference Divider Select Register
PLL is on (PLLON = 1). NOTE: The default divide value of 1 is recommended for all applications. Bit7–Bit4 — Unimplemented Bits These bits have no function and always read as logic 0s. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Clock Generator Module (CGMC)
Page 133: Interrupts
PLL clock is immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 134: Stop Mode
To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 135: Acquisition/Lock Time Specifications
Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 136: Parametric Influences On Reaction Time
External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 137: Choosing A Filter
CGMXFC CGMXFC 10 k Ω 0.01 µ F 0.47 µ F 0.033 µ F Figure 7-10. PLL Filter MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Clock Generator Module (CGMC) For More Information On This Product,...
Page 138 Freescale Semiconductor, Inc. Clock Generator Module (CGMC) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Clock Generator Module (CGMC) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 139: Section 8. Configuration Register (Config)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 8. Configuration Register (CONFIG) 8.1 Contents Introduction ........137 Functional Description .
Page 140: Configuration Register 2 (Config2)
3.6 Clock Generator Module (CGM) subsection 3.6.2 Stop Mode.) 1 = Oscillator enabled to operate during stop mode 0 = Oscillator disabled during stop mode (default) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Configuration Register (CONFIG) MOTOROLA For More Information On This Product,...
Page 141 LVI should match the operating V See Section 23. Electrical Specifications for the LVI’s voltage trip points for each of the modes. 1 = LVI operates in 5-V mode. 0 = LVI operates in 3-V mode. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA...
Page 142 COPD disables the COP module. (See Section 9. Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Configuration Register (CONFIG) MOTOROLA For More Information On This Product,...
Page 143: Section 9. Computer Operating Properly (Cop)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 9. Computer Operating Properly (COP) 9.1 Contents Introduction ........142 Functional Description .
Page 144: Introduction
(FROM CONFIG) RESET CLEAR COP COUNTER COPCTL WRITE COP RATE SEL (FROM CONFIG) Figure 9-1. COP Block Diagram Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Computer Operating Properly (COP) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 145: I/O Signals
Figure 9-1. 9.4.1 CGMXCLK CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency. 9.4.2 STOP Instruction The STOP instruction clears the COP prescaler. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Computer Operating Properly (COP) For More Information On This Product, Go to: www.freescale.com...
Page 146: Copctl Write
9.4.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. (See Section 8. Configuration Register (CONFIG).) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Computer Operating Properly (COP)
Page 147: Cop Control Register
IRQ pin, the COP is automatically disabled until a POR occurs. 9.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 148: Wait Mode
STOP instruction results in an illegal opcode reset. 9.9 COP Module During Break Mode The COP is disabled during a break interrupt when V is present on the RST pin. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Computer Operating Properly (COP) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 149: Introduction
10.2 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
Page 150: Features
• Low-power stop and wait modes 10.4 CPU Registers Figure 10-1 shows the five CPU registers. CPU registers are not part of the memory map. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Central Processor Unit (CPU) MOTOROLA For More Information On This Product,...
Page 151: Accumulator
Bit 7 Bit 0 Read: Write: Reset: Unaffected by reset Figure 10-2. Accumulator (A) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Central Processor Unit (CPU) For More Information On This Product,...
Page 152: Index Register
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 153: Program Counter
$FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Read: Write: Reset: Loaded with Vector from $FFFE and $FFFF Figure 10-5. Program Counter (PC) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA...
Page 154: Condition Code Register
H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 155 Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 156: Arithmetic/Logic Unit (Alu)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.
Page 157: Stop Mode
CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 158: Instruction Set Summary
ASR opr,SP 9E67 PC ← (PC) + 2 + rel ? (C) = 0 BCC rel Branch if Carry Bit Clear – – – – – – REL Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Central Processor Unit (CPU) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 159 – – – – – – REL PC ← (PC) + 2 + rel ? (I) = 1 BMS rel Branch if Interrupt Mask Set – – – – – – REL MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 160 0 – – 0 1 – M ← $00 CLR opr,X M ← $00 CLR ,X M ← $00 CLR opr,SP 9E6F Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Central Processor Unit (CPU) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 161 0 – – ↕ ↕ – Exclusive OR M with A EOR opr,X EOR ,X EOR opr,SP 9EE8 EOR opr,SP 9ED8 ee ff MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Central Processor Unit (CPU) For More Information On This Product,...
Page 162 H:X ← (H:X) + 1 (IX+D, DIX+) MOV X+,opr IX+D X:A ← (X) × (A) Unsigned multiply – 0 – – – 0 INH Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Central Processor Unit (CPU) MOTOROLA For More Information On This Product,...
Page 163 SP ← (SP) + 1; Pull (PCL) SP ← SP + 1 ; Pull ( PCH) Return from Subroutine – – – – – – INH SP ← SP + 1; Pull (PCL) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 164 X ← (A) Transfer A to X – – – – – – INH A ← (CCR) Transfer CCR to A – – – – – – INH Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Central Processor Unit (CPU) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 165: Opcode Map
Concatenated with ↕ Memory location Set or cleared Negative bit — Not affected 10.9 Opcode Map Table 10-2. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com...
Page 166 Freescale Semiconductor, Inc. Central Processor Unit (CPU) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Central Processor Unit (CPU) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 167: Section 11. Flash Memory
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 11. FLASH Memory 11.1 Contents 11.2 Introduction ........165 11.3...
Page 168: Flash Control Register
1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users.
Page 169: Flash Page Erase Operation
(min. 10µs) 5. Set the HVEN bit. 6. Wait for a time, t (min. 1ms) Erase 7. Clear the ERASE bit. 8. Wait for a time, t (min. 5µs) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA FLASH Memory For More Information On This Product, Go to: www.freescale.com...
Page 170: Flash Mass Erase Operation
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 171: Flash Program Operation
FLASH address programmed to clearing PGM bit (step 7 to step 10), must not exceed the maximum programming time, max. PROG This program sequence is repeated throughout the memory until all data is programmed. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 172: Flash Block Protection
The FLBPR itself can be erased or programmed only with an external voltage, V , present on the IRQ pin. This voltage also allows entry from reset into the monitor mode. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 173: Flash Programming Flowchart
PROG Clear HVEN bit This row program algorithm assumes the row/s to be programmed are initially erased. Wait for a time, t End of programming Figure 11-2. FLASH Programming Flowchart MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA FLASH Memory For More Information On This Product, Go to: www.freescale.com...
Page 174: Flash Block Protect Register
(128 bytes page boundaries) within the FLASH memory. 16-bit memory address Start address of FLASH block protect 0 0 0 0 0 0 0 FLBPR value Figure 11-4. FLASH Block Protect Start Address Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — FLASH Memory MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 175: Wait Mode
NOTE: Standby Mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is at a minimum. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 176 Freescale Semiconductor, Inc. FLASH Memory Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — FLASH Memory MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 177: Section 12. External Interrupt (Irq)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 12. External Interrupt (IRQ) 12.1 Contents 12.2 Introduction ........175 12.3...
Page 178: Functional Description
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 179: Irq Module Block Diagram
IRQ Status and Control IMASK MODE $001D Register Write: (INTSCR) Reset: = Unimplemented Figure 12-2. IRQ I/O Register Summary MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA External Interrupt (IRQ) For More Information On This Product, Go to: www.freescale.com...
Page 180: Irq Pin
The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ pin. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 181: Irq Module During Break Interrupts
• Shows the state of the IRQ flag • Clears the IRQ latch • Masks IRQ interrupt request • Controls triggering sensitivity of the IRQ interrupt pin MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA External Interrupt (IRQ) For More Information On This Product,...
Page 182: Irq Status And Control Register (Intscr)
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 183: Section 13. Keyboard Interrupt Module (Kbi)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 13. Keyboard Interrupt Module (KBI) 13.1 Contents 13.2 Introduction ........181 13.3...
Page 184: Features
• If the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 185 Freescale Semiconductor, Inc. Keyboard Interrupt Module (KBI) Functional Description MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Keyboard Interrupt Module (KBI) For More Information On This Product, Go to: www.freescale.com...
Page 186 To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 187: Keyboard Initialization
DDRA bits in data direction register A. 2. Write logic 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 188: Low-Power Modes
With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. (See 13.8.1 Keyboard Status and Control Register.) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Keyboard Interrupt Module (KBI) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 189: I/O Registers
KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 190: Keyboard Interrupt Enable Register
Reset clears the keyboard interrupt enable register. 1 = PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 191: Section 14. Low-Voltage Inhibit (Lvi)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 14. Low-Voltage Inhibit (LVI) 14.1 Contents 14.2 Introduction ........189 14.3...
Page 192: Functional Description
SIM and the LVI. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Low-Voltage Inhibit (LVI)
Page 193: Polled Lvi Operation
LVIOUT bit. In the configuration register, the LVIPWRD bit must be at logic 0 to enable the LVI module, and the LVIRSTD bit must be at logic 1 to disable LVI resets. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 194: Forced Reset Operation
[3 V]) may be lower than TRIPF TRIPF this. (See Section 23. Electrical Specifications for the actual trip point voltages.) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Low-Voltage Inhibit (LVI) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 195: Lvi Status Register
Table 14-1. LVIOUT Bit Indication LVIOUT > V TRIPR < V TRIPF < V < V Previous value TRIPF TRIPR MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Low-Voltage Inhibit (LVI) For More Information On This Product, Go to: www.freescale.com...
Page 196: Lvi Interrupts
If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 197: Section 15. Monitor Rom (Mon)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 15. Monitor ROM (MON) 15.1 Contents 15.2 Introduction ........195 15.3...
Page 198: Features
All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users.
Page 199: Monitor Mode Circuit
2. SW2, SW3, and SW4: Position C — Enter monitor mode using external oscillator. SW2, SW3, and SW4: Position D — Enter monitor mode using external XTAL and internal PLL. 3. See Table 15-1 for IRQ voltage level requirements. Figure 15-1. Monitor Mode Circuit MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 200: Entering Monitor Mode
(above condition set 1), the bus frequency is a divide-by-two of the input clock. If PTC3 is high with V applied to IRQ upon monitor mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 201 Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com...
Page 202 IRQ pin. An external oscillator of 9.8304 MHz is required for a baud rate of 9600, as the internal bus frequency is automatically set to the external frequency divided by four. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 203: Low-Voltage Monitor Mode Entry Flowchart
NOTE: Exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (POR). Pulling RST low will not exit monitor mode in this situation. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 204: Data Format
PTA0 pin high for the duration of two bits and then echoes back the break signal. MISSING STOP BIT 2-STOP BIT DELAY BEFORE ZERO ECHO Figure 15-4. Break Transaction Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Monitor ROM (MON)
Page 205: Baud Rate
9600 15.4.5 Commands The monitor ROM firmware uses these commands: • READ (read memory) • WRITE (write memory) • IREAD (indexed read) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Monitor ROM (MON) For More Information On This Product,...
Page 206: Read Transaction
1 = Echo delay, 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte. Figure 15-6. Write Transaction Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Monitor ROM (MON)
Page 207 Data None Returned Opcode Command Sequence FROM HOST ADDRESS ADDRESS ADDRESS ADDRESS WRITE WRITE DATA DATA HIGH HIGH ECHO MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com...
Page 208 Write to last address accessed + 1 Operand Single data byte Data None Returned Opcode Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Monitor ROM (MON) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 209 Table 15-9. RUN (Run User Program) Command Description Executes PULH and RTI instructions Operand None Data None Returned Opcode Command Sequence FROM HOST ECHO MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com...
Page 210: Security
FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Figure 15-8.) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Monitor ROM (MON)
Page 211: Monitor Mode Entry Timing
6 of RAM address $40 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 212 FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 213: Section 16. Input/Output (I/O) Ports
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 16. Input/Output (I/O) Ports 16.1 Contents 16.2 Introduction ........212 16.3...
Page 214: Introduction
DDRA2 DDRA1 DDRA0 Data Direction Register A $0004 Write: (DDRA) Reset: = Unimplemented Figure 16-1. I/O Port Register Summary Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Input/Output (I/O) Ports MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 215 PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0 $000F Register Write: (PTDPUE) Reset: = Unimplemented Figure 16-1. I/O Port Register Summary (Continued) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Input/Output (I/O) Ports For More Information On This Product,...
Page 216 DDRD4 ELS0B:ELS0A PTD4/T1CH0 TIM1 DDRD5 ELS1B:ELS1A PTD5/T1CH1 DDRD6 ELS0B:ELS0A PTD6/T2CH0 TIM2 DDRD7 ELS1B:ELS1A PTD7/T2CH1 DDRE0 PTE0/TxD ENSCI DDRE1 PTE1/RxD Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Input/Output (I/O) Ports MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 217: Port A
KBD7–KBD0 — Keyboard Inputs The keyboard interrupt enable bits, KBIE7–KBIE0, in the keyboard interrupt control register (KBICR) enable the port A pins as external interrupt pins. See Section 13. Keyboard Interrupt Module (KBI). MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 218: Data Direction Register A
Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 16-4 shows the port A I/O logic. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 219: Port A I/O Circuit
NOTES: 1. X = Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. 4. I/O pin pulled up to V by internal pullup device MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 220: Port A Input Pullup Enable Register
These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port A pin configured to have internal pullup 0 = Corresponding port A pin has internal pullup disconnected Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 221: Port B
PTBx/ADx pin, while PTB is read as a digital input. Those ports not selected as analog input channels are considered digital I/O ports. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 222: Data Direction Register B
WRITE DDRB ($0005) DDRBx RESET WRITE PTB ($0001) PTBx PTBx READ PTB ($0001) Figure 16-8. Port B I/O Circuit Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Input/Output (I/O) Ports MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 223 Output DDRB7–DDRB0 PTB7–PTB0 PTB7–PTB0 Notes: 1. X = Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Input/Output (I/O) Ports For More Information On This Product,...
Page 224: Port C
These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 225: Data Direction Register C
For those devices packaged in a 40-pin dual in-line package and 42-pin shrink dual in-line package, PTC5 and PTC6 are connected to ground internally. DDRC5 and DDRC6 should be set to a 0 to configure PTC5 and PTC6 as inputs. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 226: Port C I/O Circuit
1. X = Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. 4. I/O pin pulled up to V by internal pullup device. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Input/Output (I/O) Ports...
Page 227: Port C Input Pullup Enable Register
These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port C pin configured to have internal pullup 0 = Corresponding port C pin internal pullup disconnected MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 228: Port D
The edge/level select bits, ELSxB:ELSxA, determine whether the PTD7/T2CH1–PTD6/T2CH0 pins are timer channel I/O pins or general-purpose I/O pins. Section 22. Timer Interface Module (TIM). Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Input/Output (I/O) Ports MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 229 SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI is enabled, the DDRB0 bit in data direction register B (DDRB) has no effect on the PTD0/SS pin. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 230: Data Direction Register D
For those devices packaged in a 40-pin dual in-line package, PTD6 and PTD7 are not connected. DDRD6 and DDRD7 should be set to a 1 to configure PTD6 and PTD7 as outputs. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 231: Port D I/O Circuit
Notes: 1. X = Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. 4. I/O pin pulled up to V by internal pullup device. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 232: Port D Input Pullup Enable Register
0 = Corresponding port D pin has internal pullup disconnected 16.7 Port E Port E is a 2-bit special-function port that shares two of its pins with the serial communications interface (SCI) module. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 233: Port E Data Register
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. Section 18. Serial Communications Interface Module (SCI). MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 234: Data Direction Register E
Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 16-19 shows the port E I/O logic. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 235: Port E I/O Circuit
Output DDRE1–DDRE0 PTE1–PTE0 PTE1–PTE0 Notes: 1. X = Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Input/Output (I/O) Ports For More Information On This Product,...
Page 236 Freescale Semiconductor, Inc. Input/Output (I/O) Ports Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Input/Output (I/O) Ports MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 237: Section 17. Random-Access Memory (Ram)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 17. Random-Access Memory (RAM) 17.1 Contents 17.2 Introduction ........235 17.3...
Page 238 The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Random-Access Memory (RAM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 239: Module (Sci)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 18. Serial Communications Interface Module (SCI) 18.1 Contents 18.2 Introduction ........238 18.3...
Page 240: Introduction
Programmable 8-bit or 9-bit character length • Separately enabled transmitter and receiver • Separate receiver and transmitter CPU interrupt requests • Programmable transmitter output polarity Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI) MOTOROLA For More Information On This Product,...
Page 241 Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection • Configuration register bit, SCIBDSRC, to allow selection of baud rate clock source MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Serial Communications Interface Module (SCI) For More Information On This Product, Go to: www.freescale.com...
Page 242: Pin Name Conventions
The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC, of the CONFIG2 register ($001E). Source selection values are shown in Figure 18-1. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI)
Page 243: Sci Module Block Diagram
BUS CLOCK SL = 0 => X = A SL = 1 => X = B DATA SELECTION ÷ 16 CONTROL Figure 18-1. SCI Module Block Diagram MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Serial Communications Interface Module (SCI) For More Information On This Product, Go to: www.freescale.com...
Page 244: Sci I/O Register Summary
Write: (SCBR) Reset: = Unimplemented R = Reserved U = Unaffected Figure 18-2. SCI I/O Register Summary Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 245: Data Format
Figure 18-4 shows the structure of the SCI transmitter. The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC. Source selection values are shown in Figure 18-4. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 246: Sci Transmitter
CONTROL LOGIC DMATE SCTIE SCTE SCTE DMATE SCTE LOOPS SCTIE SCTIE ENSCI TCIE TCIE Figure 18-4. SCI Transmitter Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 247: Character Length
PTE0/TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port E pins. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 248: Break Characters
If the TE bit is cleared during a transmission, the PTE0/TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 249: Inversion Of Transmitted Output
SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 250: Receiver
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 251: Sci Receiver Block Diagram
SCRIE DMARE DMARE ORIE ORIE NEIE NEIE FEIE FEIE PEIE PEIE Figure 18-5. SCI Receiver Block Diagram MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Serial Communications Interface Module (SCI) For More Information On This Product, Go to: www.freescale.com...
Page 252: Data Sampling
DATA SAMPLES QUALIFICATION VERIFICATION SAMPLING CLOCK RT CLOCK STATE RT CLOCK RESET Figure 18-6. Receiver Data Sampling Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 253 Table 18-3. Data Bit Recovery RT8, RT9, and RT10 Data Bit Noise Flag Samples Determination MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Serial Communications Interface Module (SCI) For More Information On This Product,...
Page 254: Framing Errors
Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 255: Slow Data
× 4.54% ------------------------- - For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 256: Fast Data
8-bit character with no errors is · – 154 160 × 3.90% ------------------------- - Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 257: Receiver Wakeup
PTE1/RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 258: Receiver Interrupts
Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 259: Low-Power Modes
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data. Refer to Section 3. Low-Power Modes for information on exiting stop mode. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 260: Sci During Break Module Interrupts
PTE1/RxD pin with port E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE). Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 261: I/O Registers
Controls character length • Controls SCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Serial Communications Interface Module (SCI) For More Information On This Product,...
Page 262: Sci Control Register 1 (Scc1)
1 = Transmitter output inverted 0 = Transmitter output not inverted NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI)
Page 263 When enabled, the parity function inserts a parity bit in the most significant bit position. (See Figure 18-3.) Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 264: Sci Control Register 2
– Enables the TC bit to generate transmitter CPU interrupt requests – Enables the SCRF bit to generate receiver CPU interrupt requests – Enables the IDLE bit to generate receiver CPU interrupt requests Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 265: Sci Control Register 2 (Scc2)
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 266 RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 267: Sci Control Register 3
ORIE NEIE FEIE PEIE Write: Reset: = Unimplemented U = Unaffected Figure 18-11. SCI Control Register 3 (SCC3) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Serial Communications Interface Module (SCI) For More Information On This Product, Go to: www.freescale.com...
Page 268 DMARE or DMATE may adversely affect MCU performance. 1 = SCTE DMA service requests enabled; SCTE CPU interrupt requests disabled 0 = SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI)
Page 269 PE. (See 18.9.4 SCI Status Register 1.) Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 270: Sci Status Register 1
SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 271 IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 272 SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 273: Flag Clearing Sequence
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 274: Sci Status Register 2
Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI)
Page 275: Sci Data Register
Reading the SCDR accesses the read-only received data bits, R7:R0. Writing to the SCDR writes the data to be transmitted, T7:T0. Reset has no effect on the SCDR. NOTE: Do not use read/modify/write instructions on the SCI data register. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 276: Sci Baud Rate Register
Prescaler Divisor (PD) SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 18-7. Reset clears SCR2–SCR0. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI)
Page 277 PD = prescaler divisor BD = baud rate divisor Table 18-8 shows the SCI baud rates that can be generated with a 4.9152-MHz bus clock when f is selected as SCI clock source. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 278 9600 4800 2400 1200 25,600 12,800 6400 3200 1600 19,200 9600 4800 2400 1200 5908 2954 1477 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Communications Interface Module (SCI) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 279: Section 19. System Integration Module (Sim)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 19. System Integration Module (SIM) 19.1 Contents 19.2 Introduction ........278 19.3...
Page 280: Introduction
• CPU enable/disable timing • Modular architecture expandable to 128 interrupt sources Table 19-1 shows the internal signal names used in this section. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — System Integration Module (SIM) MOTOROLA For More Information On This Product,...
Page 281: Sim Block Diagram
(Bus clock = CGMOUT divided by two) Internal address bus Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal Read/write signal MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com...
Page 282: Sim I/O Register Summary
IF16 IF15 Interrupt Status Register 3 $FE06 Write: (INT3) Reset: = Unimplemented Figure 19-2. SIM I/O Register Summary Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — System Integration Module (SIM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 283: Sim Bus Clock Control And Generation
19.3.2 Clock Startup from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 284: Clocks In Stop Mode And Wait Mode
(see 19.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 19.8 SIM Registers.) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — System Integration Module (SIM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 285: External Pin Reset
Number of Cycles Required to Set PIN POR/LVI 4163 (4096 + 64 + 3) All others 67 (64 + 3) CGMOUT VECT H VECT L Figure 19-4. External Reset Timing MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com...
Page 286: Active Resets From Internal Sources
INTERNAL RESET Figure 19-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — System Integration Module (SIM)
Page 287: Power-On Reset
OSC1 PORRST 4096 CYCLES CYCLES CYCLES CGMXCLK CGMOUT IRST $FFFE $FFFF Figure 19-7. POR Recovery MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com...
Page 288: Computer Operating Properly (Cop) Reset
ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 289: Low-Voltage Inhibit (Lvi) Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 290: Sim Counter During Stop Mode Recovery
(I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 291: Interrupt Entry Timing
SP – 3 SP – 2 SP – 1 PC + 1 PC – 1 [15:8] PC – 1 [7:0] OPCODE OPERAND Figure 19-9. Interrupt Recovery Timing MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com...
Page 292: Interrupt Processing
LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION INSTRUCTION? UNSTACK CPU REGISTERS INSTRUCTION? EXECUTE INSTRUCTION Figure 19-10. Interrupt Processing Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — System Integration Module (SIM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 293: Hardware Interrupts
If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 294: Swi Instruction
SCI receive error IF11 SCI receive IF12 SCI transmit IF13 Keyboard IF14 ADC conversion complete IF15 Lowest Timebase module IF16 Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — System Integration Module (SIM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 295: Interrupt Status Register 1 (Int1)
IF14–IF7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from the sources shown in Table 19-3. 1 = Interrupt request present 0 = No interrupt request present MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA...
Page 296: Reset
(TIM).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 297: Status Flag Protection In Break Mode
CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 298: Wait Mode Entry Timing
Figure 19-16. Wait Recovery from Interrupt or Break CYCLES CYCLES $6E0B RST VCT H RST VCT L CGMXCLK Figure 19-17. Wait Recovery from Internal Reset Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — System Integration Module (SIM) MOTOROLA For More Information On This Product,...
Page 299: Stop Mode
PREVIOUS DATA NEXT OPCODE SAME SAME Note : Previous data can be operand data or the STOP opcode, depending on the last instruction. Figure 19-18. Stop Mode Entry Timing MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com...
Page 300: Sim Registers
SBSW Write: Note Reset: = Reserved Note: Writing a logic 0 clears SBSW. Figure 19-20. SIM Break Status Register (SBSR) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — System Integration Module (SIM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 301 ;then just decrement low byte. HIBYTE,SP ;Else deal with high byte, too. DOLO LOBYTE,SP ;Point to WAIT/STOP opcode. RETURN PULH ;Restore H register. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA System Integration Module (SIM) For More Information On This Product,...
Page 302: Sim Reset Status Register
0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 303: Sim Break Flag Control Register
MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 304 Freescale Semiconductor, Inc. System Integration Module (SIM) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — System Integration Module (SIM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 305: Section 20. Serial Peripheral Interface Module (Spi)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 20. Serial Peripheral Interface Module (SPI) 20.1 Contents 20.2 Introduction ........304 20.3...
Page 306: Introduction
Programmable wired-OR mode • C (inter-integrated circuit) compatibility • I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Peripheral Interface Module (SPI) MOTOROLA For More Information On This Product,...
Page 307: Pin Name Conventions
Read: SPI Data Register $0012 Write: (SPDR) Reset: Unaffected by reset = Unimplemented Figure 20-1. SPI I/O Register Summary MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Serial Peripheral Interface Module (SPI) For More Information On This Product, Go to: www.freescale.com...
Page 308: Spi Module Block Diagram
If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. (See 16.5.3 Port C Input Pullup Enable Register.) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Peripheral Interface Module (SPI)
Page 309: Master Mode
MISO SHIFT REGISTER MOSI MOSI SHIFT REGISTER SPSCK SPSCK BAUD RATE GENERATOR Figure 20-3. Full-Duplex Master-Slave Connections MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Serial Peripheral Interface Module (SPI) For More Information On This Product, Go to: www.freescale.com...
Page 310: Slave Mode
SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 311: Transmission Formats
SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 312: Transmission Format When Cpha = 0
The slave’s SS pin must be toggled back to high and then low again between each byte transmitted as shown in Figure 20-5. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Peripheral Interface Module (SPI)
Page 313: Transmission Format (Cpha = 0)
SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 314: Transmission Format When Cpha = 1
BIT 3 BIT 2 BIT 1 FROM SLAVE SS; TO SLAVE CAPTURE STROBE Figure 20-6. Transmission Format (CPHA = 1) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Peripheral Interface Module (SPI) MOTOROLA For More Information On This Product,...
Page 315: Transmission Initiation Latency
SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 316: Transmission Start Delay (Master)
TO SPDR CLOCK SPSCK = INTERNAL CLOCK ÷ 128; EARLIEST LATEST 128 POSSIBLE START POINTS Figure 20-7. Transmission Start Delay (Master) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Peripheral Interface Module (SPI) MOTOROLA For More Information On This Product,...
Page 317: Queuing Transmission Data
Also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 318: Error Conditions
Clear the overflow flag by reading the SPI status and control register and then reading the SPI data register. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 319: Missed Read Of Overflow Condition
SPRF was cleared and that future transmissions can set the SPRF bit. Figure 20-10 illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 320: Mode Fault Error
For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 321 When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and later unselected (SS is at logic 1) even if no SPSCK is sent to that MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 322: Interrupts
(DMAS = 0, SPRIE = 1) OVRF SPI receiver/error interrupt request (ERRIE = 1) Overflow MODF SPI receiver/error interrupt request (ERRIE = 1) Mode fault Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Peripheral Interface Module (SPI) MOTOROLA For More Information On This Product,...
Page 323: Spi Interrupt Request Generation
NOT AVAILABLE SPRIE SPRF SPI RECEIVER/ERROR CPU INTERRUPT REQUEST ERRIE MODF OVRF Figure 20-11. SPI Interrupt Request Generation MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Serial Peripheral Interface Module (SPI) For More Information On This Product, Go to: www.freescale.com...
Page 324: Resetting The Spi
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 325: Low-Power Modes
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 326: Spi During Break Interrupts
MOSI — Data transmitted • SPSCK — Serial clock • SS — Slave select • CGND — Clock ground (internally connected to V Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Peripheral Interface Module (SPI) MOTOROLA For More Information On This Product,...
Page 327: Miso (Master In/Slave Out)
MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 328: Spsck (Serial Clock)
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high- impedance state. The slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 329: Cgnd (Clock Ground)
20.13.5 CGND (Clock Ground) CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It is internally connected to V shown in Table 20-1. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 330: I/O Registers
SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 331 This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 20.10 Resetting the SPI.) Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA...
Page 332: Spi Status And Control Register
SPTE ERRIE MODFEN SPR1 SPR0 Write: Reset: = Unimplemented Figure 20-14. SPI Status and Control Register (SPSCR) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Peripheral Interface Module (SPI) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 333 (SPSCR) with MODF set and then writing to the SPI control register (SPCR). Reset clears the MODF bit. 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 334 In master mode, these read/write bits select one of four baud rates as shown in Table 20-4. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Peripheral Interface Module (SPI)
Page 335: Spi Data Register
Figure 20-15. SPI Data Register (SPDR) R7–R0/T7–T0 — Receive/Transmit Data Bits NOTE: Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 336 Freescale Semiconductor, Inc. Serial Peripheral Interface Module (SPI) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Serial Peripheral Interface Module (SPI) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 337: Section 21. Timebase Module (Tbm)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 21. Timebase Module (TBM) 21.1 Contents 21.2 Introduction ........335 21.3...
Page 338: Functional Description
0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Figure 21-1. Timebase Block Diagram Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Timebase Module (TBM) MOTOROLA For More Information On This Product,...
Page 339: Timebase Register Description
Timebase Interrupt Rate TBR2 TBR1 TBR0 Divider 32768 1000 8192 2048 62.5 ~ 3.9 1024 2048 ~0.5 4096 ~0.24 MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Timebase Module (TBM) For More Information On This Product, Go to: www.freescale.com...
Page 340: Interrupts
TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Interrupts must be acknowledged by writing a logic 1 to the TACK bit. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 341: Low-Power Modes
STOP mode. In stop mode the timebase register is not accessible by the CPU. If the timebase functions are not required during stop mode, reduce the power consumption by stopping the timebase before enabling the STOP instruction. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 342 Freescale Semiconductor, Inc. Timebase Module (TBM) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Timebase Module (TBM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 343: Section 22. Timer Interface Module (Tim)
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 22. Timer Interface Module (TIM) 22.1 Contents 22.2 Introduction ........342 22.3...
Page 344: Introduction
• Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIM counter stop and reset bits Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Timer Interface Module (TIM) MOTOROLA For More Information On This Product,...
Page 345: Pin Name Conventions
If a channel is configured as input capture, then an internal pullup device may be enabled for that channel. (See 16.6.3 Port D Input Pullup Enable Register.) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 346: Tim Block Diagram
NOTE: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC and T2SC. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 347: Tim I/O Register Summary
TOV1 CH1MAX $0028 and Control Register Write: (T1SC1) Reset: = Unimplemented Figure 22-2. TIM I/O Register Summary (Sheet 1 of 3) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Timer Interface Module (TIM) For More Information On This Product,...
Page 348 Register High Write: (T2CH0H) Reset: Indeterminate after reset = Unimplemented Figure 22-2. TIM I/O Register Summary (Sheet 2 of 3) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Timer Interface Module (TIM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 349: Tim Counter Prescaler
TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 350: Output Compare
Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 351: Buffered Output Compare
TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 352: Unbuffered Pwm Signal Generation
PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 353: Buffered Pwm Signal Generation
TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 354: Pwm Initialization
PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 355: Interrupts
CHxIE = 1. CHxF and CHxIE are in the TIM channel x status and control register. 22.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 356: Wait Mode
BCFE is at logic 0. After the break, doing the second step clears the status bit. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 •...
Page 357: I/O Signals
• TIM counter registers (TCNTH:TCNTL) • TIM counter modulo registers (TMODH:TMODL) • TIM channel status and control registers (TSC0, TSC1) • TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Timer Interface Module (TIM) For More Information On This Product,...
Page 358: Tim Status And Control Register
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Timer Interface Module (TIM)
Page 359 Internal bus clock ÷ 2 Internal bus clock ÷ 4 Internal bus clock ÷ 8 Internal bus clock ÷ 16 Internal bus clock ÷ 32 Internal bus clock ÷ 64 Not available MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA...
Page 360: Tim Counter Registers
Bit 0 Read: Bit 7 Bit 0 Write: Reset: = Unimplemented Figure 22-6. TIM Counter Registers Low (TCNTL) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Timer Interface Module (TIM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 361: Tim Counter Modulo Registers
Bit 7 Bit 0 Write: Reset: Figure 22-8. TIM Counter Modulo Register Low (TMODL) NOTE: Reset the TIM counter before writing to the TIM counter modulo registers. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Timer Interface Module (TIM) For More Information On This Product, Go to: www.freescale.com...
Page 362: Tim Channel Status And Control Registers
ELS1B ELS1A TOV1 CH1MAX Write: Reset: = Unimplemented Figure 22-10. TIM Channel 1 Status and Control Register (TSC1) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Timer Interface Module (TIM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 363 MSxA — Mode Select Bit A When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. Table 22-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA...
Page 364 Toggle output on compare Buffered output Clear output on compare compare or buffered PWM Set output on compare Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Timer Interface Module (TIM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 365: Tim Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 366: Tim Channel 0 Register High (Tch0H)
Read: Bit 7 Bit 0 Write: Reset: Indeterminate after reset Figure 22-15. TIM Channel 1 Register Low (TCH1L) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Timer Interface Module (TIM) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 367: Section 23. Electrical Specifications
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 23. Electrical Specifications 23.1 Contents 23.2 Introduction ........366 23.3...
Page 368: Introduction
V or V . Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either V or V Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Electrical Specifications MOTOROLA For More Information On This Product,...
Page 369: Functional Operating Range
2. K is a constant unique to the device. K can be determined for a known T and measured . With this value of K, P and T can be determined for any value of T MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 370: V Dc Electrical Characteristics
C Out — — Ports (as input or output) C In — — Monitor mode entry voltage + 2.5 — Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Electrical Specifications MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 371 9. Maximum is highest voltage that POR is possible. 10. If minimum V is not reached before the internal POR reset is released, RST must be driven low externally until minimum is reached. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 372: V Dc Electrical Characteristics
C Out — — Ports (as input or output) C In — — Monitor mode entry voltage + 2.5 — Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Electrical Specifications MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 373 9. Maximum is highest voltage that POR is possible. 10. If minimum V is not reached before the internal POR reset is released, RST must be driven low externally until minimum is reached. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 374: V Control Timing
8. The minimum period, t or t , should not be less than the number of cycles it takes to ILIL TLTL execute the interrupt service routine plus t Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Electrical Specifications MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 375: V Control Timing
8. The minimum period, t or t , should not be less than the number of cycles it takes to ILIL TLTL execute the interrupt service routine plus t MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA...
Page 376: Output High-Voltage Characteristics
= –0.6 mA > V –1.0 V @ I = –4.0 mA Figure 23-2. Typical High-Side Driver Characteristics – Port PTA7–PTA0 (V = 2.7 Vdc) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Electrical Specifications MOTOROLA For More Information On This Product,...
Page 377 –20 –25 > V –0.5 V @ I = –4.0 mA Figure 23-4. Typical High-Side Driver Characteristics – Port PTC4–PTC0 (V = 2.7 Vdc) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Electrical Specifications For More Information On This Product,...
Page 378 –1.0 V @ I = –4.0 mA Figure 23-6. Typical High-Side Driver Characteristics – Ports PTB7–PTB0, PTC6–PTC5, PTD7–PTD0, and PTE1–PTE0 (V = 2.7 Vdc) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Electrical Specifications MOTOROLA For More Information On This Product,...
Page 379: Output Low-Voltage Characteristics
< 0.3 V @ I = 0.5 mA < 1.0 V @ I = 6.0 mA Figure 23-8. Typical Low-Side Driver Characteristics – Port PTA7–PTA0 (V = 2.7 Vdc) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Electrical Specifications For More Information On This Product, Go to: www.freescale.com...
Page 380 = 4.5 Vdc) –40 < 0.8 V @ I = 10 mA Figure 23-10. Typical Low-Side Driver Characteristics – Port PTC4–PTC0 (V = 2.7 Vdc) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Electrical Specifications MOTOROLA For More Information On This Product,...
Page 381 < 0.3 V @ I = 0.5 mA < 1.0 V @ I = 6.0 mA Figure 23-12. Typical Low-Side Driver Characteristics – Ports PTB7–PTB0, PTC6–PTC5, PTD7–PTD0, and PTE1–PTE0 (V = 2.7 Vdc) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Electrical Specifications For More Information On This Product, Go to: www.freescale.com...
Page 382: Typical Supply Currents
Turned On (–40 °C to 85 °C) 5.5 V 3.6 V (MHz) Figure 23-14. Typical Wait Mode I , with all Modules Disabled (–40 °C to 85 °C) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Electrical Specifications MOTOROLA For More Information On This Product,...
Page 383 1.10 5.5 V 1.05 3.6 V (MHz) Figure 23-15. Typical Stop Mode I , with all Modules Disabled (–40 °C to 85 °C) MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Electrical Specifications For More Information On This Product,...
Page 384: Adc Characteristics
3. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 4. The external system error caused by input leakage current is approximately equal to the product of R source and input current. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 385: V Spi Characteristics
70% V , unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 386: V Spi Characteristics
, unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • —...
Page 387 MASTER LSB OUT OUTPUT Note: This last clock edge is generated internally, but is not seen at the SPSCK pin. b) SPI Master Timing (CPHA = 1) Figure 23-16. SPI Master Timing MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • —...
Page 388 MSB IN LSB IN INPUT Note: Not defined but normally LSB of character previously transmitted b) SPI Slave Timing (CPHA = 1) Figure 23-17. SPI Slave Timing Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Electrical Specifications MOTOROLA For More Information On This Product,...
Page 389: Timer Interface Module Characteristics
— k Ω Series resistor — — Notes: 1. When using crystals between 30kHz and 100kHz, use fundamental mode crystals only. 2. Consult crystal manufacturer’s data. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Electrical Specifications For More Information On This Product,...
Page 390: Cgm Electrical Specifications
1.5 M PLL enabled Notes: 1. 5.0 V ± 10% V 2. 3.0 V ± 10% V 3. Deviation of average bus frequency over 2 ms. N = VCO multiplier. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Electrical Specifications MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 391: Memory Characteristics
7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 392 Freescale Semiconductor, Inc. Electrical Specifications Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Electrical Specifications MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 393: Section 24. Mechanical Specifications
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Section 24. Mechanical Specifications 24.1 Contents 24.2 Introduction ........391 24.3...
Page 394: Pin Plastic Dual In-Line Package (Pdip)
0.600 BSC 15.24 BSC 0° 15° 0° 15° 0.020 0.040 0.51 1.02 42 PL 42 PL 0.25 (0.010) 0.25 (0.010) Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Mechanical Specifications MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 395: Pin Plastic Quad Flat Pack (Qfp)
0.005 — 0° — 0° — 12.95 13.45 0.510 0.530 DETAIL C 0.40 — 0.016 — 1.6 REF 0.063 REF MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA Mechanical Specifications For More Information On This Product, Go to: www.freescale.com...
Page 396 Freescale Semiconductor, Inc. Mechanical Specifications Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Mechanical Specifications MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 397: Section 25. Ordering Information
MC Order Numbers ....... . 395 25.2 Introduction This section contains ordering numbers for the MC68HC908GP32. 25.3 MC Order Numbers Table 25-1.
Page 398 Freescale Semiconductor, Inc. Ordering Information Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — Ordering Information MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 399: Appendix A. Mc68Hc08Gp32
Freescale Semiconductor, Inc. Technical Data – MC68HC908GP32•MC68HC08GP32 Appendix A. MC68HC08GP32 A.1 Contents Introduction ........398 MCU Block Diagram .
Page 400: Introduction
Freescale Semiconductor, Inc. MC68HC08GP32 A.2 Introduction This section introduces the MC68HC08GP32, the ROM part equivalent to the MC68HC908GP32. The entire data book apply to this ROM device, with exceptions outlined in this appendix. Table A-1. Summary of MC68HC08GP32 and MC68HC908GP32 differences MC68HC08GP32 MC68HC908GP32 Memory ($8000–$FDFF)
Page 401 Freescale Semiconductor, Inc. MC68HC08GP32 MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA MC68HC08GP32 For More Information On This Product, Go to: www.freescale.com...
Page 402: Memory Map
The MC68HC08GP32 has 32,256 bytes of user ROM from $8000 to $FDFF, and 36 bytes of user ROM vectors from $FFDC to $FFFF. On the MC68HC908GP32, these memory locations are FLASH memory. Figure A-2 shows the memory map of the MC68HC08GP32.
Page 403: Mask Option Registers
Figure A-4) are read-only registers. They are defined by mask options (hard-wired connections) specified at the same time as the ROM code submission. On the MC68HC908GP32, these two registers are called configuration registers (CONFIG2 and CONFIG1). MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data •...
Page 404: Reserved Registers
A.6 Reserved Registers The two registers at $FE08 and $FF7E are reserved locations on the MC68HC08GP32. On the MC68HC908GP32, these two locations are the FLASH control register and the FLASH block protect register respectively. A.7 Monitor ROM The monitor program (monitor ROM, $FE20–$FF52) on the MC68HC08GP32 is for device testing only.
Page 405: Electrical Specifications
Freescale Semiconductor, Inc. MC68HC08GP32 A.8 Electrical Specifications Electrical specifications for the MC68HC908GP32 apply to the MC68HC08GP32, except for the parameters indicated below. A.8.1 Functional Operating Range Characteristic Symbol Value Unit ° C Operating temperature range – 40 to +85 – 40 to +105 –...
Page 406: V Dc Electrical Characteristics
No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs. 7. Measured with TBM enabled using 32kHz crystal. 5.5 V 3.3 V (MHz) Figure A-5. Typical Operating I Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — MC68HC08GP32 MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 407: Memory Characteristics
A.8.4 Memory Characteristics Characteristic Symbol Unit RAM data retention voltage — Notes: Since MC68HC08GP32 is a ROM device, FLASH memory electrical characteristics do not apply. MC68HC908GP32 MC68HC08GP32 Rev. 6 Technical Data • — MOTOROLA MC68HC08GP32 For More Information On This Product,...
Page 408: Rom Mc Order Numbers
–40 ° C to +105 ° C MC68HC08GP32VFB 44-pin QFP –40 ° C to +125 ° C MC68HC08GP32MFB Notes: 1. Temperature grade "M" is available for 5V operating voltage only. Technical Data MC68HC908GP32 MC68HC08GP32 Rev. 6 • — MC68HC08GP32 MOTOROLA For More Information On This Product,...
Page 409 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com...
Page 410 All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as...

Motorola MC68HC908GP32 Technical Data Manual

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32

Table of Contents

Table of Contents

Section 1. General Description

Section 2. Memory Map

Section 3. Low-Power Modes

Low-Power Modes

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 4. Resets and Interrupts

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 5. Analog-To-Digital Converter (Adc)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 6. Break Module (Brk)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 7. Clock Generator Module (Cgmc)

Section 7. Clock Generator Module (CGMC)

Section 8. Configuration Register (CONFIG)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 9. Computer Operating Properly (Cop)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 10. Central Processor Unit (Cpu)

Section 10. Central Processor Unit (CPU)

Section 11. FLASH Memory

Section 13. Keyboard Interrupt Module (KBI)

Section 15. Monitor ROM (MON)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 16. Input/Output (I/O) Ports

Section 16. Input/Output (I/O) Ports

Section 17. Random-Access Memory (RAM)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 18. Serial Communications Interface Module (Sci)

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Summary of Contents for Motorola MC68HC908GP32