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• V-RAM Write Timing
1. When the CPU emits the MWR signal, the 1/0 READY signal becomes disabled, and the
CPU then enters wait state.
2. The pin 8 of U1 becomes HIGH at the falling edge of the
siC
signal. In this case, if the pin
5 of U5 is HIGH and the CPU is in memory write mode, the OE signal of the 6116
becomes lOW.
Then the data sent from the CPU is written to the 6116.
3. The 1/0 READY signal becomes HIGH at the rising edge of the CRTC-ClK signal. When
the CPU cycle is changed from TW cycle to T4 cycle, the MWR signal becomes HIGH. Then
an impedance of the I/O READY signal becomes high.
97
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