Sony DVW-A500P Maintenance Manual page 63
Digital videocassette recorder
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Also See for DVW-A500P:
- Maintenance manual (524 pages) ,
- Manuel de fonctionnement (164 pages) ,
- User manual (157 pages)
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[CIRCUIT DESCRIPTION OF DPR-36 BOARD]
DPR-36 board is a digital processor board that encodes the
recording digital data and decodes the playback digital data.
The recording process is described below.
The recording video data ("REC data 0 through 9") sent from
VPR-1 board is input to encoder IC (IC6), where the video
data is field-shuffled via memory (IC1100 through IC1102 (or
IC9 through IC20 for the board with suffix 11 through 14)),
then compressed to the data rate of approximately 1/2 by a
newly developed bit rate reduction process.
After that, outer error correction code (ECC) is added to the
video data, and the data is track-interleaved via memory (IC21
through IC24).
The recording audio data ("ENC 1/2 and 3/4") sent from the
audio data processor IC (IC69) described later are also input
to the encoder IC via IC905.
Outer ECCs are added to the audio data, and the data are
field-shuffled via a part of the memory (IC21 through IC24)
mentioned above.
In this process, the video data and audio data are
multiplexed.
The multiplexed data is added ID data, inner ECC encoded,
then added sync data.
The two groups of REC data ("REC AC D0 through D3" and
"REC BD D0 through D3") generated as described above are
sent to EQ-45 board for RF processing together with REC
ENABLE signals for each head.
All the encoding processes mentioned above are performed
by IC6 and IC905.
All the encoding processes are completed in one field.
This thus causes no trouble during editing.
Next, the playback process is described below.
The two groups of AC/BD ADVANCE PB data and
CONFIDENCE PB data sent from EQ-45 board are input in
parallel to two inner ECC decoder ICs (IC29 and IC38).
The REC data bypassed from the output of the encoder IC
for diagnosis execution is also input.
Each inner ECC decoder IC selects a necessary data from
these input data, detects the sync data, performs the inner
correction based on the detected sync data, then extracts the
ID information.
Based on the extracted ID information, each inner ECC
decoder performs the clock rate transfer and de-interleaving
for the data via memory (IC30, 31, 33, and 34, and IC39, 40,
42, and 43).
In this process, the two groups of data are multiplexed, then
separated into V data and V/A data.
They are sent to outer ECC decoder ICs (IC35 and IC44)
with each error flag data added.
In IC35, the video data is outer-corrected, de-shuffled via
memory (IC76 through IC79 (or IC36 and IC37 for the board
suffix 11 through 13)), then sent to video decoder IC (IC45).
The audio data is outer-corrected, de-shuffled via internal
memory, then error-concealed.
The resultant data is transferred the clock rate, then sent to
the audio data processing system.
DVW-A500/500
DVW-A500P/500P
As described above, an ECC decoder consists of an inner
ECC decoder and an outer ECC decoder.
Two pairs of ECC decoders are installed in this unit, and one
pair decodes only the audio data.
Such constitution is arranged to obtain both the audio data
before erasure and the inserted audio data during editing and
insertion.
This enables the confidence playback for cross-fading during
audio editing.
The video data input to the video decoder IC is decoded by
the bit rate reduction process so as to return to the former
data rate, and de-shuffled via memory (IC1103 through IC1105
(or IC51 through IC62 for the board with suffix 11 through
14)). The data is then error-concealed via FIFO memory (IC63
through IC67) and sent to VPR-1 board as video PB data
("PB DATA 0 through 9").
Lastly, the audio data processing system is described below.
IC69 and IC911 are the audio data processor.
For the recording audio data, "AD R 1/2 and 3/4", and
"AES R 1/2 and 3/4" data are sent from APR-1 board, and
"SIF R 1/2 and 3/4" data are sent from DIF-16 board, all in the
form of serial audio data two by two audio channels.
The audio data processor performs the audio data selection,
gain control, REC verification, and other data processing, then
converts the resultant data into the recording audio data
("ENC 1/2 and 3/4") and sends them to the encoder IC.
In the PB mode, the decoded audio data is sent to IC73.
IC73 is a jog audio processor.
It compensates the noise during jog or shuttle using external
memory (IC74), and sends data to the audio data processor.
The audio data processor performs the gain control, phase
adjustment, muting, and other data processing.
It then converts the resultant data into serial audio data
"DA T 1/2 and 3/4", "MONI L/R", "AES T 1/2 and 3/4", and
sends them to APR-1 board. In addition, it converts the data
into serial audio data "SIF T 1/2 and 3/4", and sends it to DIF-
16 board.
3-19
DPR-36
DPR-36
3-19
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