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Yamaha LSI YMF744B Technical Manual

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OVERVIEW
YMF744B (DS-1S) is a high performance audio controller for the PCI Bus. DS-1S consists of two separated
functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block
allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine.
The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without
utilizing the CPU or causing system latency. By using the Software Driver from YAMAHA, PCI Audio
provides 64-voice XG wavetable synthesizer with Reverb and variation. It also supports DirectSound hardware
accelerator, Downloadable Sound (DLS) and DirectMusic accelerator.
Legacy Audio block supports FM Synthesizer, Sound Blaster Pro, MPU401 UART mode and Joystick
function in order to provide hardware compatibility for numerous PC games on real DOS without any software
driver. To achieve legacy DMAC compatibility on the PCI, DS-1S supports both PC/PCI and Distributed
DMA protocols. DS-1S also supports Serialized IRQ for legacy IRQ compatibility.
DS-1S supports the connection to AC'97 which provides high quality DAC, ADC and analog mixing, and it
can connect two AC'97s. In addition, it supports consumer IEC958, Audio Digital Interface (SPDIF), to
connect external audio equipment by digital.
FEATURES
• PCI 2.2 Compliant
• PC'98/PC'99 specification Compliant
• PCI Bus Power Management rev. 1.0 Compliant
(Support D0, D2 and D3 state)
• Supports clock run
• PCI Bus Master for PCI Audio
True Full Duplex Playback and Capture with
different Sampling Rate
Maximum 64-voice XG capital Wavetable
Synthesizer including GM compatibility
DirectSound Hardware Acceleration
DirectMusic Hardware Acceleration
Downloadable Sound (DLS) level-1
• Legacy Audio compatibility
FM Synthesizer
Hardware Sound Blaster Pro compatibility
MPU401 UART mode MIDI interface
Joystick
• Supports Serialized IRQ
The contents of this catalog are target specifications and are subject to change
without prior notice. When using this device, please recheck the specifications.
YMF744B
DS-1S
YAMAHA CORPORATION
• Supports PC/PCI and Distributed DMA for legacy
DMAC (8237) emulation
2
• Supports I
S serial input for Zoomed Video Port
• Supports Consumer IEC958 Output (SPDIF OUT)
• Supports Consumer IEC958 Input (SPDIF IN)
• Supports AC'97 Interface (AC-Link) Revision 2.1
• AC'97 Digital Docking
• Supports 4-Channel Speaker
• Hardware Volume Control
• EEPROM Interface
• Single Crystal operation (24.576MHz)
• 3.3V Power supply (5V tolerant)
• 128-pin LQFP
YMF744B-V : 0.5mm pin pitch
YMF744B-R : 0.4mm pin pitch
CATALOG No.:LSI-4MF744B00
Preliminary
YMF744B CATALOG
December 18, 1998
February 3, 1999

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  • Page 1 The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without utilizing the CPU or causing system latency. By using the Software Driver from YAMAHA, PCI Audio provides 64-voice XG wavetable synthesizer with Reverb and variation. It also supports DirectSound hardware accelerator, Downloadable Sound (DLS) and DirectMusic accelerator.
  • Page 2 MIDI functions. 2. XG XG is a format about MIDI synthesizer that is proposed by YAMAHA, and keeps the upper compatibility of GM system level 1. The good points are the voice arrangements kept extensively, a large number of the voices, modification of the voices, 3 kinds of effects, and so on.

  • Page 3: Pin Configuration

    YMF744B PIN CONFIGURATION YMF744B-V (0.5mm pin pitch) AD26 TEST# PVDD2 VDD2 AD25 VSS3 AD24 VDD1 CBE3# CMCLK IDSEL CSDO AD23 CBCLK PVSS4 CSDI0 AD22 CSYNC AD21 CRST# AD20 VDD0 AD19 VSS2 AD18 RESERVE2 AD17 RESERVE3 AD16 CSDI2 CBE2# DOCKEN# PVSS3 VSS1 FRAME# XI24...
  • Page 4 YMF744B YMF744B-R (0.4mm pin pitch) AD24 VDD1 CBE3# CMCLK IDSEL CSDO AD23 CBCLK PVSS4 CSDI0 AD22 CSYNC AD21 CRST# AD20 VDD0 AD19 VSS2 AD18 RESERVE2 AD17 RESERVE3 AD16 CSDI2 CBE2# DOCKEN# PVSS3 VSS1 FRAME# XI24 IRDY# XO24 TRDY# LOOPF DEVSEL# LVDD PVDD1 CVDD1...

  • Page 5: Pin Description

    YMF744B PIN DESCRIPTION 1. PCI Bus Interface (54-pin) Name Type Size Function PCICLK PCI Clock RST# Reset AD[31:0] Address / Data C/BE[3:0]# Command / Byte Enable Parity FRAME# Pstr Frame IRDY# Pstr Initiator Ready TRDY# Pstr Target Ready STOP# Pstr Stop IDSEL ID Select...
  • Page 6 YMF744B 3. External Audio Interface (5-pin) Name Type Size Function SPDIFOUT Digital Audio Interface output SPDIFIN Digital Audio Interface input ZVBCLK Zoomed Video Port Bit Clock ZVLRCK Zoomed Video Port L/R Clock ZVSDI Zoomed Video Port Serial Data 4. Legacy Device Interface (15-pin) Name Type Size...
  • Page 7 YMF744B 6. Power Supply (22-pin) Name Type Size Function PVDD[3:0] 3.3V Power supply for PCI Bus Interface PVSS[6:0] Ground for PCI Bus Interface CVDD[2:0] 3.3V Power supply for Core logic VDD[2:0] 3.3V Power supply VSS[3:0] Ground LVDD 3.3V Power supply for PLL Filter 7.

  • Page 8: Block Diagram

    YMF744B BLOCK DIAGRAM EEPROM I/F SPDIF Input GPIO ZV Port SPDIF Output PCI Side Band Legacy Audio PC/PCI FM Synthesizer S-IRQ SB Pro D-DMA Engine MPU401 Interface Sampling Joystick Converter AC-Link PCI Bus Master Interface DMA Controller Audio Revision2.1 Function Config Register PCI Native Audio...

  • Page 9: Function Overview

    YMF744B FUNCTION OVERVIEW 1. PCI INTERFACE DS-1S supports the PCI bus interface and complies to PCI revision 2.2. 1-1. PCI Bus Command DS-1S supports the following PCI Bus commands. 1-1-1. Target Device Mode C/BE[3:0]# Command Interrupt Acknowledge (not support) Special Cycle (not support) I/O Read I/O Write reserved...
  • Page 10 Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro, MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation. The following shows the overview of the PCI Configuration Register.
  • Page 11 Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit Vendor ID b[15:0] ..Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.2. This register is hardwired to 1073h. 02-03h: Device ID Read Only Default: 0010h Access Bus Width: 8, 16, 32-bit Device ID b[15:0] ..Device ID...
  • Page 12 YMF744B b6....PER: Parity Error Response This bit enables DS-1S responses to Parity Error. “0”: DS-1S ignores all parity errors. “1”: DS-1S performs error operation when DS-1S detects a parity error. b8....SER: SERR# Enable This bit enables DS-1S to drive SERR#. “0”: Do not drive SERR#.
  • Page 13 YMF744B 08h: Revision ID Read Only Default: 02h Access Bus Width: 8, 16, 32-bit Revision ID b[7:0] ..Revision ID This register contains the revision number of DS-1S. This register is hardwired to 02h. 09h: Programming Interface Read Only Default: 00h Access Bus Width: 8, 16, 32-bit Programming Interface b[7:0] ..Programming Interface...
  • Page 14 YMF744B 0Dh: Latency Timer Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit Latency Timer b[7:0] ..Latency Timer When DS-1S becomes a Bus Master device, this register indicates the initial value of the Master Latency Timer. 0Eh: Header Type Read Only Default: 00h Access Bus Width: 8, 16, 32-bit...
  • Page 15 YMF744B 14-17h: Legacy Audio I/O Base Address (Dummy for SB, FM, MPU, D-DMA) Read / Write Default: 00000001h Access Bus Width: 8, 16, 32-bit IOBASE0 b0....IO (Read Only) This bit indicates that the base address is assigned to I/O. This bit is hardwired to “1”. b[15:6] ..IOBASE0 This register is used so that the OS may secure I/O resources for Sound Blaster Pro, FM Synthesizer, MPU401 and D-DMA controller.
  • Page 16 In case of the system such as Sound Card which BIOS can not control, this ID can be changed by connecting EEPROM externally. Then, Subsystem Vendor ID Write Register is invalid. In case EEPROM is not externally, the default value is the YAMAHA's Vendor ID, 1073h. 2E-2Fh: Subsystem ID...
  • Page 17 YMF744B 34h: Capability Register Pointer Read Only Default: 50h Access Bus Width: 8, 16, 32-bit Capability Register Pointer b[7:0] ..Capability Register Pointer This register indicates the offset address of the Capabilities register in the PCI Configuration register when 58-59h: ACPI Mode register, ACPI bit is “0”. DS-1S provides PCI Bus Power Management registers as the capabilities.
  • Page 18 YMF744B 3Fh: Maximum Latency Read Only Default: 19h Access Bus Width: 8, 16, 32-bit Maximum Latency b[7:0] ..Maximum Latency This register indicates how often DS-1S generates the Bus Master Request. This register is hardwired to 19h. 40-41h: Legacy Audio Control Read / Write Default: 907Fh Access Bus Width: 8, 16, 32-bit...
  • Page 19 YMF744B b4....MIEN: MPU401 IRQ Enable This bit enables the interrupt service of MPU401, when LAD is set to “0” and MEN is set to “1”. MPU401 generates an interrupt signal when it receives any kind of MIDI data from the RXD pin. “0”: The MPU401 block can not use the interrupt service.
  • Page 20 YMF744B b14....SIEN: Serialized IRQ enable DS-1S supports 3 types of interrupt protocols: PCI interrupt (INTA#), Legacy interrupt (IRQs) and Serialized IRQ. The interrupt protocol is selected with IMOD and SIEN as follows. The interrupt channels for IRQs and Serialized IRQ are determined by SBIRQ and MPUIRQ,. Only one protocol can be used at once.
  • Page 21 ..Subsystem Vendor ID Write Register This register sets the Subsystem Vendor ID that is read from 2C-2Dh (Subsystem Vendor ID register). The default value is the YAMAHA Vendor ID, 1073h. IHVs must change this ID to their Vendor ID in the BIOS POST routine.
  • Page 22 YMF744B 48-49h: DS-1S Control Read / Write Default: 0001h Access Bus Width: 8, 16, 32-bit ACLS WRST CRST b0....CRST: AC’97 Software Reset Signal Control This bit controls the CRST# signal. “0”: Inactive (CRST#=High) “1”: Active (CRST#=Low) (default) b2....WRST: AC’97 Warm Reset This bit places the AC’97 in warm reset condition when the BIT_CLK signal on the AC’97 remains in inactive state.
  • Page 23 YMF744B 4A-4Bh: DS-1S Power Control 1 Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit DPLL b0....DMC: Disable Master Clock Oscillation Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz). “0”: Normal (default) “1”: Disable b2....DPLL: Disable PLL Clock Oscillation Setting this bit to “1”...
  • Page 24 YMF744B b12....PR4: AC’97 Power Down Control 4 This bit controls the power state of the AC-link in the Primary AC’97. “0”: Normal (default) “1”: Power down b13....PR5: AC’97 Power Down Control 5 Setting this bit to “1” disables the internal clock of the Primary AC’97. In case the AC’97 is used with DS-1S, the master clock is supplied from DS-1S.
  • Page 25 YMF744B 4E-4Fh: DS-1S Power Control 2 Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit PSHWV PSIO PSACL PSDIR PSDIT PSZV PSSRC PSPCA PSJOY PSMPU PSSB PSFM CMCD b0....CMCD: CODEC Master Clock Disable Setting this bit to “1” disables the oscillation of the CMCLK. To stop a clock, when the CMCLK is supplied to the AC’97, it is required that b13:PR5 bit of 4A-4Bh register is set to “1”.
  • Page 26 YMF744B b7....PSZV: Power Save Zoomed Video port Setting this bit to “1” stops a clock supplied to the Zoomed Video port block. “0”: Normal (default) “1”: Disable b8....PSDIT: Power Save Digital Audio Interface Transmitter Setting this bit to “1” stops a clock supplied to the DIT block. “0”: Normal (default) “1”: Disable...
  • Page 27 YMF744B CMCD AC97 Master Clock PSFM FM Synthesizer PSSB SB Pro PSMPU MPU401 PSJOY Joystick PSPCA Master PCI Audio Clock PSSRC (24.576MHz) PSZV ZVport DPLL PSDIT SPDIF out PSDIR SPDIF in PSHWV H/W Vol. PSACL AC-link PCI I/F PC/PCI Clock S-IRQ (33MHz) EEPROM I/F...
  • Page 28 YMF744B 51h: Next Item Pointer Read Only Default: 00h Access Bus Width: 8, 16, 32-bit Next Item Pointer b[7:0] ..Next Item Pointer DS-1S does not provide other new capability besides Power Management. This register is hardwired to 00h. 52-53h: Power Management Capabilities Read Only Default: 0401h Access Bus Width: 8, 16, 32-bit...
  • Page 29 YMF744B 58-59h: ACPI Mode Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit ACPI b0....ACPI: ACPI Mode Select This bit select either PCI Bus Power Management or ACPI Mode for power management of DS-1S. “0”: PCI Bus Power Management is used. CAP bit (06-07h: Status Register) and Capabilities Pointer (34h) are enabled.
  • Page 30 YMF744B b4....SPR4: Secondary AC’97 Power Down Control 4 This bit controls the power state of the AC-link in the Secondary AC’97. “0”: Normal (default) “1”: Power down b5....SPR5: Secondary AC’97 Power Down Control 5 Setting this bit to “1” disables the internal clock of the Secondary AC’97. In case the AC’97 is used with DS-1S, the master clock is supplied from DS-1S.
  • Page 31 YMF744B 64-65h: MPU401 Base Address Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit MPU401 Base Address b[15:1] ..MPU401 Base Address This register sets the base address of the MPU401. If b5:I/O bit of 40h register is set to “1”, b[9:1] bits are decoded by ignoring b[15:10] bits.
  • Page 32 The configuration is set in the Legacy Audio Control Register in the PCI Configuration Register space. Basically, these registers are configured by the BIOS. Also, logical device IDs are assigned to the devices to support Plug and Play. Yamaha defines the following logical IDs.
  • Page 33 DS-1S supports PC/PCI and D-DMA protocols to emulate the DMA of SB Pro on the PCI. In addition, DS- 1S supports the old type of interrupts used by ISA and the Serialized IRQ protocol. Yamaha recommends the combination of PC/PCI and Serialized IRQ. The system block diagram when using Intel chip set is shown below.
  • Page 34 YMF744B 2-1. FM Synthesizer Block FM Synthesizer Block is register compatible with YMF289B. However, Power Management register has been deleted because it is now controlled by the PCI Configuration Register. The following shows the FMBase I/O map of FM Synthesizer. FMBase Status Register port FMBase...
  • Page 35 YMF744B 2-1-2. FM Synthesizer Data Register FM Synthesizer Data Register Array 0 (R/W): Address 00-01h LSI TEST TIMER 1 TIMER 2 (*1) 20-35h MULT (*2) 40-55h (*3) 60-75h (*4) 80-95h A0-A8h F-NUM (L) B0-B8h BLOCK F-NUM (H) C0-C8h (*5) E0-F5h FM Synthesizer Data Register Array 1 (R/W) Address 00-01h...
  • Page 36 YMF744B 2-2. Sound Blaster Pro Block This block emulates the DSP commands of Sound Blaster and Sound Blaster Pro. Only playback functions are supported (record functions are not supported). However, to maintain compatibility for games, it is designed so that every DSP command receives a correct response. The DMA transfer of this block uses PC/PCI or D-DMA protocol.
  • Page 37 YMF744B 2-2-1. DSP Command The following shows the list of DSP Commands that are supported by the SB Pro engine. Both SB and SB Pro commands are supported. CMD Support Function 8bit direct mode single byte digitized sound output 8bit single-cycle DMA mode digitized sound output 8bit to 2bit ADPCM single-cycle DMA mode digitized sound output 8bit to 2bit ADPCM single-cycle DMA mode digitized sound output with ref.
  • Page 38 YMF744B 2-2-2. Sound Blaster Pro Mixer The following shows the register map of the Mixer section of Sound Blaster Pro. Address Remark Reset Voice Volume L "1" Voice Volume R "1" "1" MIC Volume* Ifilter* Input Source* "1" "1" Ofilter* "1"...
  • Page 39 YMF744B (1) Volume for MIDI MIDI Vol. (26h) mute mute mute mute mute mute mute mute 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h mute -52dB -42dB -36dB -32dB -30dB -28dB -26dB 0000h 0029h 0082h 0103h 019Bh 0206h 028Ch 0335h mute -42dB -32dB...
  • Page 40 YMF744B 2-2-3. SB Suspend / Resume The SB block can read the internal state as to support Suspend and Resume functions. The internal state is made up of 268 flip flops. To read the state, these states are shifted in order and read 8 bits at a time from the SCAN DATA register.
  • Page 41 YMF744B F1h: Scan In/ Out Data Read / Write Default: 00h SCAN DATA b[7:0] ..SCAN DATA This is the data port for reading and writing the internal state. F2h: Current FM Synthesizer Index Read Only Default: 00h Current FM Synthesizer Index b[7:0] ..Current FM Synthesizer Index This register indicates current index of the FM Synthesizer.
  • Page 42 YMF744B b7....FFEMP: FM Synthesizer Empty This bit indicates whether or not FIFO followed by the FM Synthesizer is empty. “0”: not Empty “1”: Empty (default) i) Scan Out ii) Scan In : not ready for scanning : not ready for scanning SBPDA=0 SBPDA=0 internal state data...
  • Page 43 YMF744B 2-2-4. SB IRQ Status F8h: Interrupt Flag Register Read Only Default: 00h b0....SBI: SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt. This bit is read only. Thus, read the SB DSP read port to clearing the interrupt and this bit. Then, the value of the read port is invalid. 2-3.
  • Page 44 YMF744B 3. DMA Emulation Protocol The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller (8237: ISA DMAC) on the system to transfer the sound data from/to the host. For DS-1S, however, ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of the Legacy Audio Block.
  • Page 45 YMF744B 3-2. D-DMA DS-1S provides the following registers to support D-DMA. D-DMA Slave Configuration Register (4C- 4Dh) of the PCI Configuration register is used to set the Base address of the Slave Address. Slave Address Register Name Base + 0h Base Address 0-7 Base + 0h Current Address 0-7...

  • Page 46: Interrupt Routing

    YMF744B 4. Interrupt Routing DS-1S supports three types of interrupts, interrupt signal on the PCI bus (INTA#), interrupt signal on the ISA bus (IRQ[5,7,9,10,11]), and Serialized IRQ. The IRQs on DS-1S are routed as shown below. PCI Audio INTA# INTA SIEN=0, IMOD=1 SIEN=0, IMOD=0 Sound Blaster Pro...
  • Page 47 YMF744B 5. Hardware Volume Control The hardware volume control determines the AC’97 master volume without using any software control using the external circuit listed below. Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used. Push SW VOLUP# Push SW...

  • Page 48: Digital Audio Interface

    YMF744B 6. Digital Audio Interface DS-1S supports each system of the SPDIF input/output port compliant with the IEC958 specification. 6-1. SPDIF IN DS-1S provides the SPDIF input capability by switch-over operation of the zoomed video port. SPDIF input sampling frequency is 32.0kHz, 44.1kHz or 48.0kHz. In DS-1S, sampling rate of the SPDIF signal incoming from the SPDIFIN pin is converted to 48.0kHz in the frequency rate conversion stage in order to process all the signals at 48.0kHz frequency.

  • Page 49: Zoomed Video Port

    YMF744B 7. Zoomed Video Port Zoomed Video Port is defined in the PC Card Standard (PCMCIA) applicable to the notebook PC or other systems. This port is used to directly output video and/or audio signals onto the PCMCIA bus for D/A conversion process, and connect them directly to the video and/or audio signal processing chips on the PC system.
  • Page 50 YMF744B 8. Multiple AC’97 & Multi-Channel DS-1S allows connection with up to two AC’97s, and plays back up to 4-channel PCM data. Therefore, the following applications can be realized. 8-1. AC’97 Digital Docking AC’97 digital docking can be realized by mounting the secondary AC’97 on the docking station side. Typical example of digital docking connection between DS-1S and AC’97s is represented in the circuit diagram below.

  • Page 51: Electrical Characteristics

    YMF744B ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Item Symbol Min. Max. Unit Power Supply Voltage -0.3 (PVDD, VDD, CVDD, LVDD) Input Voltage -0.3 Operating Ambient Temperature °C Storage Temperature °C Note : PVSS=VSS=0[V] 2. Recommended Operating Conditions Item Symbol Min. Typ.
  • Page 52 YMF744B 3. DC Characteristics Item Symbol Condition Min. Typ. Max. Unit High Level Input Voltage 1 -0.5 5.75 High Level Input Voltage 1 0.5V 5.75 Low Level Input Voltage 1 -0.5 0.3V High Level Input Voltage 2 0.7V 5.75 Low Level Input Voltage 2 -0.5 0.3V High Level Input Voltage 3...
  • Page 53 YMF744B 4. AC Characteristics 4-1. Master Clock (Fig.1) Item Symbol Min. Typ. Max. Unit XI24 Cycle Time 40.69 XICYC XI24 High Time XIHIGH XI24 Low Time XILOW Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V 2.3 V 1.65 V XI24...
  • Page 54 YMF744B 4-3. PCI Interface (Fig.3, 4) Item Symbol Condition Min. Typ. Max. Unit PCICLK Cycle Time PCYC PCICLK High Time PHIGH PCICLK Low Time PLOW PCICLK Slew Rate V/ns (Bused signal) PVAL PCICLK to Signal Valid Delay (Point to Point) PVAL(PTP) Float to Active Delay Active to Float Delay...
  • Page 55 YMF744B 4-4. AC’97 Master Clock (Fig.5) Item Symbol Min. Typ. Max. Unit CMCLK Cycle Time 40.69 CMCYC CMCLK High Time CMHIGH CMCLK Low Time CMLOW CMCLK Rising Time CMCLK Falling Time Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, C =50 pF 0.8 V 0.5 V...
  • Page 56 YMF744B 4-5. AC-link (Fig.6) Item Symbol Condition Min. Typ. Max. Unit CBCLK Cycle Time 81.4 CBICYC CBCLK High Time 40.7 CBIHIGH CBCLK Low Time 40.7 CBILOW CSYNC Cycle Time 20.8 CSYCYC CSYNC High Time µs CSYHIGH CSYNC Low Time 19.5 µs CSYLOW CBCLK to Signal Valid Delay...
  • Page 57 YMF744B 4-6. Zoomed Video Port (Fig.7) Item Symbol Min. Typ. Max. Unit ZVLRCK Delay Time SLRD ZVLRCK Setup Time SLRS ZVBCLK Low Time SCLKL ZVBCLK High Time SCLKH ZVSDI Setup Time ZVSDI Hold Time Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, C =50 pF ZVLRCK SLRS...

  • Page 58: External Dimensions

    Plastic body dimensions do not include burr of resin. UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. For detailed information, please contact your nearest agent of Yamaha. February 3, 1999 -58-...
  • Page 59 Plastic body dimensions do not include burr of resin. UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. For detailed information, please contact your nearest agent of Yamaha. February 3, 1999 -59-...

  • Page 60: Important Notice

    YMF744B IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document.

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