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7.
IC DESCRIPTIONS
7.1
PD4290C
7.1.1.
Main CPU Port Arrangement PD4290C (BLE & Main Control)
| O
PD4290C
|
POWEROFF
it
64M
GND
SENS-T
2
63M = RM-MS
SIOENABLE in
3
e2i— = AM-UP
SENS-S
4
61 = AM-DOWN
AE-3
a 5
60 5
AM-SLOW
AE-2
Ms
50M = -RM-R
AE
7
58M
RM-L
AE-O
|S
s7M-RM-PLAY 1
METER-R
a 9
56 a
RM-PLAY 2
METER-L
10
SSM
3 kHz MUTE
BLEMODE = 1
S415 kHz MUTE
SIOREG out
= 12
53
BIAS
SUB CPU RESET
a 13
52 a
METER
RESET
OSciPWM
14
Si
BIAS-2
si
15
SoM
BIAS-3
mere so
a 16
49 a
BIAS-—4
SCK out
17
48M
BIAS-5
VR A/D IN
18
47M
OSC1
4 so aanizy
LEVEL-3
19
4s = 0sc2
LEVEL-2
20
45
RESET
LEVEL~-1
a
44
AD-4
LEVEL-o
22
43M
AD-5
High EQ-1
23
42
BIAS-0/-UP
HighEQ-0
24
41 =
BIAS-1/-DOWN
TAPE
M25
40M
AD-0
LEVEL-4
26
30m
AD-1
Mid EQ-3
27
36M
AD-2
MidEQ-2
28
37M
AD-3
MidEQ-1
20
36M
SONG
MidEQ-0
30
35
PBMUTE
sv
st
34
REC MUTE
+5V
B32
338
LINE MUTE
7.1.2
WO Matrix Table
¢ Output standard value for setting
LEVEL (Sbit): 01111
Mid EQ (4bit) : 0111
High EQ (2bit) : According to the table above.
45
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