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Logic Symbology
A-33.
FLIP-FLOP.
A-34.
The symbol for a flip-flop is shown in figure A-l2.
The letters "FF" preceded by the name of the flip-flop dis-
tinguish this symbol from other types of multivibrators. Ad-
ditional identification, described later, identifies the particu-
lar type of flip-flop.
A-35.
A flip-flop is a bistable switching device; an ex-
ternal signal is required to set the flip-flop and another to
clear it. The flip-flop remains in its current state until
switched to the opposite state by the appropriate external
signal. Various forms of flip-flops exist, of which seven are
described here: the R-S (reset-set), clocked R-S, J-K, clocked
J-K, toggle, latch, and delay flip-flops.
7900-117
DIRECT SET
INTT
SET
----f--'--.......-II---_
SET OUTPUT
CLOCK
- - - i
l
C
FF
CLEAR
----LI--r-_ _
-1~t----
CLEAR OUTPUT
I
DIRECT CLEAR
INPUT
Figure A-l2. General Flip-Flop Logic Symbol
A-36.
R-S FLIP-FLOP. The symbol for the R-S flip-flop
as shown in figure A-l3 can be recognized by the fact that
there is no information in the symbol identifying it as one
of the other six types. The R-S flip-flop has a minimum of
two input terminals (A and B in figure A-l3) and one or
two output terminals Q and
Q.
One or two additional input
terminals, C and D, may be used.
A-37.
The R-S flip-flop is set by a high input at A (as-
suming no inverting dot at this point).
It
can also be set by a
high input at C, if this input terminal is present. The flip-
flop is cleared by a high input at B or D. Figure A-l3 in-
cludes a truth table, showing the flip-flop outputs resulting
from various input conditions.
A
L
H
L
H
7900-118
A-4
C
:=-j
:
I
FF
Q
Q
D
INPUT
OUTPUT
B
0
I
5
L
No Change
L
H
I
L
H
L
H
H
I ndeterm inate
I
Figure A-l3. R-S Flip-Flop, Logic Symbol,
and Truth Table
790lA
A-3S.
After being set or cleared, the R-S flip-flop remains
in that condition after termination of the set or clear pulse.
If
the flip-flop is either set or clear and it receives an input
to place it in the existing state no change takes place in the
state of the flip-flop.
A-39.
Simultaneous high set and clear input signals norm-
ally. are not permitted, and circuit design usually prevents
occurrence of this condition at a time when the flip-flop
outputs are used.
If
simultaneous set and clear inputs are re-
ceived, both outputs of the flip-flop are high for the dura-
tion of the simultaneous inputs. The eventual state of the
flip-flop is determined by the input that remains longest in
the activating condition.
A-40.
CLOCKED R-S FLIP-FLOP. The clocked R-S flip-
flop is similar to the R-S flip-flop, but it has a clock pulse
input as shown in figure A-l4. The logic symbol can be rec-
ognized by the letter "C" at this inPl:lt terminal. At the
positive-going transition of the clock pulse, the flip-flop be-
comes set if input A is high, or it becomes clear if input B is
high (assuming no inverting dot at the clock pulse input
terminal).
If
inputs A and B are both low during the clock
pulse, the flip-flop does not change state.
It
is not permis-
sible that A and B both be high when the positive-going
clock pulse transition. takes place.
~ ---~I
C --F-F-1-_ _ _ _
~
A-.J
B
C
I~
U~
Q
l
7900-119
Figure A-14. Clocked R-S Flip-Flop, Logic Symbol,
and Switching Waveforms
A-41.
When the clocked R-S flip-flop has an inverting
dot at the clock pulse input (figure A-l5), the negative-
going transition of the clock pulse is the transition that
is effective in setting or clearing the flip-flop.
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