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Ij2~5
4K UV
P~OM
MOdule
13255-91007/08
Rev
AUG-Ol-7&
3.6.2
The heart ot this circuit is the 93L10 counter.
When PROM SELECT
is low, the counter is reset so that QO=Ql=y2=Q3=O, and the differing
inputs on
U310
will cause the outputs of the two exclusive-or gates
to be high.
Two gates are uSed for the output to the signal WAIT
to provide the current sinking capabilities required for bus signals
(note that a 74LS38 would normally be used in this situation).
When PROM SE:LECT goes high, indicating that data from one Of the
PROMs is to be read, the following sequence takes place:
Q3
02
01
00
CEP
PE
WAIT
----.-------~-------------~-------~------
0
0
0
0
1
1
1
0
0
0
0
1
1
t
1
0
0
0
1
0
1
1
1
0
0
0
1
1
1
1
1
0
0
1
0
()
1
1
1
0
0
1
0
1
1
1
0
0
1
0
0
0
1
0
1
1
The time during which WAIT is low corresponds to 6 clock cycles
=
1.2 microseconds.
when the last state is reached the counter will
remain 1n this state, since eET is low, until PROM SELECT goes low,
reseting the counter to the initial state.
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