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(U15,
U16,
U17B).
The
control circuitry and the
gate-
time generator are sequentially gated
by
a
1-kHz
clock.
A
measurement cycle for the frequency
counter begins
with a START
pulse
from
PIA line
CA2. This
pulse
resets the gate-time generator
and clears
the accumu-
lator via the control circuitry (U16A
and
Ul6B).
On the
next
cycle of the
1-kHz clock,
the accumulator
input
gate (U17B)
is
enabled
by
the control circuitry
(U15A).
The accumulator
will
total
the
cycles
of the
unknown
signal
until the time-out of the gate timer or
until
an
accumulator
overflow
is detected by
U8D,
U17 A, and
Ul7C.
This
will
disable
the
accumulator input
and
signal the
processor
(via
the PIA
pin,
CAl)
that
the
count
is
complete.
The processor, in
turn,
disables the
AID
output
drivers,
switches the
DVM/
COUNTER
BUFFER
to
the counter
mode,
and
inputs the 16-bit
accumulator information.
The
gate-time generator
provides
gate times ofO.OOl,
0.01
, 0.1,
1,
and
10
seconds,
which translate to resolu-
tions
of
1000, 100, 10, 1,
and 0.1
Hz. These
gate
times
are user-selectable or can
be
auto-selected by
the pro-
cessor to give a
5-digit
frequency
display with
a
reso-
lution
of0.1
Hz.
13.2.3.3
Period Counter
The period
counter consists of a
clock
generator
(U46-U49),
a
positive-edge detector
(U39B), control
circuitry
(U36-40),
and the same
accumulator, buffer,
and
PIA as
the frequency
counter.
The
control'
circui-
try
is
sequentially gated at
the
same
rate as the clock
generator.
A
period-counter
measurement begins with
a START
pulse
from PIA line CA2. This pulse clears
the accumulator
(Ul8,
Ul9) and control circuitry
(U38,
U39A).
The period
counter then waits for U39B to
detect
a
positive rising
edge of the unknown signal.
When
a
positive
edge
is detected,
the control circuitry
will enable the accumulator input gate (U40B).
The
accumulator will count
the cycles
of the
period-counter
clock
until
the
next positive
rising edge of one period
of the
unknown
signals.
This
will
disable
the
accumu-
lator input
and signal the processor (via
PIA pin
CAl)
that
the count
is
complete. The
processor
will then
input the data
as
described
above for the frequency
counter.
The
period-counter
clock
generator (U47 -U49) takes
the
RF
Synthesizer's
10-MHz signal
and
divides it
down
to 1
MHz
and
100 kHz. These
three signals (10
MHz,
1
MHz,
and
100
kHz) are selected and sent to
the counter
by
switch
U46.
These
clock
rates produce
period-counter resolutions
of
0.1 Hz, 1
Hz,
10 Hz, 100
Hz,
and 1
kHz. The
resolutions
are user-selectable or
can
be
auto-selected
by
the
processor.
13.2.4
BOARD CONTROL
The
processor
on the
AF
control
bus controls this
board.
The 4-bit
address
(AF
ADD BUS
0-3)
is
decoded
by
the address
decoder
(U5,
U33,
U43) to
determine
in which control
latch
(U6,
U7,
or
U42)
the
control
data is
to
be
stored.
The
four data
bits
(AF
DATA BUS
0-3) are then stored
in
the selected con-
trol latch
hy
a
pulse
on the AF
BUS EN
2
line.
1
3-3
/( 13-4 blank)
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