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Power-Down Control Division Diagram; Explanation Of Each Bit - Yamaha YMF795 Manual

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YMF795

■Power-down control division diagram

Power-down of the LSI can be controlled for each divided internal function.

The power-down is controlled by Index 38h.

SCLK

SYNC

Serial

I/F

SDIN

/IRQ

/RST

■Explanation of each bit

DP0

This is the bit to power off the whole digital section.

Consumption current of the digital part can be minimized because internal clock stops.

Contents of the registers are held but data in the FIFO are cleared.

AP1

This is the bit to power off the VREF circuit.

If AP1 is set to "1", the whole analog section stops. Because an analog center voltage is made by VREF circuit.

AP2

This is the bit to power off the FM volume section, EQ circuit, speaker volume, and non-inverted amplifier side of

speaker output section.

Controlled by

using DP bit

Timing Generator

Synthesizer

RAM

Simultaneous

Sound

FIFO

Generation

4-tone

16b × 32w

Controlled by

using AP1 bit

-21-

Controlled by

using AP4 bit

VOL

32-step

VOL

32-step

DAC

VOL

32-step

VREF

Controlled by

using AP3 bit

Controlled by

using AP2 bit

EQ1

EQ2

EQ3

SPOUT1

AMP

SPOUT2

SPVSS

Table of Contents

Power-Down Control Division Diagram; Explanation Of Each Bit - Yamaha YMF795 Manual

■Power-down control division diagram

■Explanation of each bit

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Table of Contents