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Instruction
Decoding
Additional
Information on
Instruction
Decoding
Note
IJ
HP 103140
The HP 10314D Preprocessor Interface will send all of the bus
transactions by both the microprocessor and coprocessor to the logic
analyzer. The time count will accurately reflect when the end of the
bus cycle occurred. No distinction is made between instructions that
are executed and those that are only prefetched by the microprocessor.
Typically, several states separate the memory (or
1/0)
transfer from the
instruction that caused the transfer.
The logic analyzer is clocked once each bus cycle. The preprocessor
interface hardware ensures that the logic analyzer will reliably capture
the address, data, and status information during both pipelined and
non-pipelined cycles by latching this information during the current bus
cycle and sending it to the logic analyzer during the succeeding bus
cycle. See the "Preprocessor Interface Description" section in chapter
3 for complete details of this process.
A 32-bit memory cycle on a 16-bit bus is sent to the logic analyzer as
two bus transactions.
The preprocessor interface stops generating logic analyzer clocks when
the 80386DX asserts HLDA. Bus cycles that assert HLDA, such as
DMA cycles, will not be captured by the logic analyzer.
To disable the HLDA line from stopping the logic analyzer clocks,
move the jumper on J9 to the ON position (see figure 2-6). This will
bypass the HLDA control on the preprocessor interface leaving the
preprocessor interface active (ON) for all bus cycles.
The ADS and READY lines must be operating in normal 80386DX
bus cycles when the HLDA line is disabled. If these lines are not
present during the HLDA (hold acknowledge) period, the
preprocessor interface will not remain in step with following bus cycles.
This will result in incorrect capturing of data.
80386DX Preprocessor Interface
Analyzing the Intel 80386DX
2-13
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