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Award BIOS Setup
3.6 Advanced Chipset Features
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
access to system memory resources, such as DRAM and the external
cache. It also coordinates communications between the conventional ISA
bus and the PCI bus. It must be stated that these items should never need
to be altered. The default settings have been chosen because they provide
the best operating conditions for your system. The only time you might
consider making any changes would be if you discovered that data was
being lost while using your system.
CMOS Setup Utility – Copyright © 1984 – 2001 Award Software
SDRAM CAS Latency Time
SDRAM Cycle Time Tras/Trc
SDRAM RAS-to-CAS Delay
SDRAM RAS Precharge Time
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
CPU Latency Timer
Delayed Transaction
CRT LCD Switch
AGP Graphics Aperture Size
Disk On Chip Address
↑↓←→Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values
SDRAM CAS Latency Time:
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing.
The choice: 2, 3
SDRAM Cycle Time Tras/Trc:
Select the number of SCLKs for an access cycle.
The choice: 5/7, 7/9 and Auto.
All manuals and user guides at all-guides.com
Advanced Chipset Features
3
Auto
Auto
Auto
Disabled
Disabled
Disabled
Enabled
Enabled
CRT Only
64MB
DC000H-DFFFFH
F6: Fail-safe defaults
40
Item Help
____________________________
Menu Level
F7: Optimized Defaults
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