Table of Contents
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1 OVERVIEW
Pin name Pin No.
Type
#RDRC
10
Open-drain
output
Schmitt
trigger input
#RDET
11
Output
PDWN
12
Input
#RESET
13
Input
V
14
Power
SS
supply (-)
OSC3
15
Input
OSC4
16
Output
EXTCLK
17
Input
MODE0
18
Input
MODE1
19
Input
#PQUAL
20
Output
4
Power-down
status
Active
Ring Detect RC Terminal: RC network will be connected to this pin
to set time delays for the ring signal detection. This circuit is always
active even if the device is in the power down mode.
Active
Ring Detect Output: When the MODE1 pin is set to low level, this pin
is connected from output of a Schmitt trigger buffer which input is
connected to the #RDRC pin. Low level at this pin indicates that the
ring signal is detected. When the MODE1 pin bit is set to high level,
this pin is connected from output of a hook detect circuit which input is
connected from the HOOK pin. High level at this pin indicates on-hook
condition and low level at this pin indicates off-hook condition.
Active
Power Down Input: This pin must be kept at low level for the normal
operation. When it is set to high level, the device enters the power
down mode. During power down mode, the OSC4 pin is set to high
level, and the V
(The FB and V
MODE1 pin is at low level.)
Active
Reset Input: When this pin is set to low level, all internal host
registers are reset to their default conditions. This pin must be set to
high level to write data to the internal registers.
Device Ground: This pin is connected to the system ground.
Off
Crystal Oscillator/External Clock Input: A crystal resonator is
connected between this pin and the OSC4 pin. This pin may be driven
from an external clock source. The proper value load capacitor must
be connected between this pin and ground. During power down, this
input pin is disconnected from internal circuits.
High level Crystal Oscillator Output: A crystal or ceramic resonator is
connected between this pin and OSC3 pin. This pin must be kept
open when the OSC3 pin is driven from an external clock source. The
proper value load capacitor must be connected between this pin and
ground. During power down, this output pin is set to high level.
Active
External Clock Input: Typically 32.768 kHz clock signal is applied to
this pin from the host device to enable pre-qualification logic used in
FSK energy detection circuitry.
Active
Mode0 Select Input: This pin select CAS or FSK/CPM mode. When
this pin is set to high level, CAS mode is selected. In this mode, CAS
detection is enabled and the FSK function is disabled. The host
device also can write internal registers through the SDI and #SCLK
pin. Before writing data into registers, this pin must be set to low level
once to synchronize the serial interface circuit for data writing
sequence. When this pin is set to low level, FSK/CPM mode is
selected. In this mode, CAS detection is disabled and the FSK/CPM
function is enabled. The host device also can read the received data
from the SDO pin under this mode. Refer to Table 3.2.1 for more
details.
Active
Mode1 Select Input: This pin enables FSK energy and off-hook
detection mode. When this pin is set to high level, FSK energy and
off-hook detection mode is enabled. When this pin is set to low level,
FSK energy and off-hook detection mode is disabled. Refer to Table
3.2.1 for more details.
High level Pre-qualification Output: Early qualification output will be monitored
at this pin. When no tones are detected, this pin stays at high level.
EPSON
Description
, CASFB and FB pins are set to high impedance.
REF
pins are set to high impedance only when the
REF
S1C05251 TECHNICAL MANUAL
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