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Motorola PowerQUICC II MPC8280 Series Reference Manual

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Table of Contents

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Freescale Semiconductor, Inc.
MPC8280RM
3/2004, Rev. 0
MPC8280 PowerQUICC II™ Family
Reference Manual
Supports MPC8270
MPC8275
MPC8280
For More Information On This Product,
Go to: www.freescale.com

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Summary of Contents for Motorola PowerQUICC II MPC8280 Series

  • Page 1 Freescale Semiconductor, Inc. MPC8280RM 3/2004, Rev. 0 MPC8280 PowerQUICC II™ Family Reference Manual Supports MPC8270 MPC8275 MPC8280 For More Information On This Product, Go to: www.freescale.com...
  • Page 2 Motorola makes no warranty, representation or guarantee regarding the suitability of its products Tai Po Industrial Estate, Tai Po, N.T., Hong Kong for any particular purpose, nor does Motorola assume any liability arising out of the application or 852-26668334 use of any product or circuit, and specifically disclaims any and all liability, including without TECHNICAL INFORMATION CENTER: limitation consequential or incidental damages.
  • Page 3 Freescale Semiconductor, Inc. Part I—Overview Overview G2_LE Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port For More Information On This Product, Go to: www.freescale.com...
  • Page 4 Freescale Semiconductor, Inc. Part I—Overview Overview G2_LE Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port For More Information On This Product, Go to: www.freescale.com...
  • Page 5 Freescale Semiconductor, Inc. Part IV—Communications Processor Module Communications Processor Module Overview Serial Interface with Time-Slot Assigner CPM Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels and IDMA Emulation Serial Communications Controllers (SCCs) SCC UART Mode SCC HDLC Mode SCC BISYNC Mode SCC Transparent Mode SCC Ethernet Mode SCC AppleTalk Mode...
  • Page 6 Freescale Semiconductor, Inc. Part IV—Communications Processor Module Communications Processor Module Overview Serial Interface with Time-Slot Assigner CPM Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels and IDMA Emulation Serial Communications Controllers (SCCs) SCC UART Mode SCC HDLC Mode SCC BISYNC Mode SCC Transparent Mode SCC Ethernet Mode SCC AppleTalk Mode...

  • Page 7: Table Of Contents

    Communications Processor Module (CPM) ............ 1-8 Software Compatibility Issues ................1-9 1.3.1 Signals......................1-9 Differences between MPC860 and MPC8280........... 1-10 Serial Protocol Table..................1-11 MPC8280 Configurations .................. 1-11 1.6.1 Pin Configurations ..................1-12 MOTOROLA Contents For More Information On This Product, Go to: www.freescale.com...
  • Page 8 Hardware Implementation-Dependent Register 0 (HID0) ....2-12 2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1) ....2-15 2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2) ....2-15 2.3.1.2.4 Processor Version Register (PVR)............2-16 viii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 9 Acronyms and Abbreviations ................II-2 Chapter 4 System Interface Unit (SIU) System Configuration and Protection ..............4-2 4.1.1 Bus Monitor ..................... 4-4 4.1.2 Timers Clock....................4-4 4.1.3 Time Counter (TMCNT).................. 4-5 MOTOROLA Contents For More Information On This Product, Go to: www.freescale.com...
  • Page 10 Time Counter Register (TMCNT) ............. 4-45 4.3.2.16 Time Counter Alarm Register (TMCNTAL)..........4-46 4.3.3 Periodic Interrupt Registers ................4-47 4.3.3.1 Periodic Interrupt Status and Control Register (PISCR) ......4-47 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 11 Contents ......................III-1 Suggested Reading..................... III-2 MPC82xx Documentation ................. III-2 Conventions ....................... III-2 Acronyms and Abbreviations ................III-2 Chapter 6 External Signals Functional Pinout ....................6-1 Signal Descriptions ....................6-2 MOTOROLA Contents For More Information On This Product, Go to: www.freescale.com...
  • Page 12 7.2.5.2 Address Retry (ARTRY)................7-11 7.2.5.2.1 Address Retry (ARTRY)—Output ............7-11 7.2.5.2.2 Address Retry (ARTRY)—Input ............7-12 7.2.6 Data Bus Arbitration Signals ................. 7-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 13 Transfer Type Signal (TT[0–4]) Encoding ..........8-10 8.4.3.2 Transfer Code Signals TC[0–2] ..............8-13 8.4.3.3 TBST and TSIZ[0–3] Signals and Size of Transfer ........8-13 8.4.3.4 Burst Ordering During Data Transfers ............8-14 MOTOROLA Contents xiii For More Information On This Product, Go to: www.freescale.com...
  • Page 14 Addressing ....................9-9 9.9.1.2.3 Byte Enable Signals................9-10 9.9.1.2.4 Bus Driving and Turnaround ..............9-10 9.9.1.3 Bus Transactions..................9-10 9.9.1.3.1 Read and Write Transactions ..............9-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 15 PCI Error Control Capture Register (PCI_ECCR) ........9-44 9.11.1.15 PCI Inbound Translation Address Registers (PITARx) ......9-45 9.11.1.16 PCI Inbound Base Address Registers (PIBARx) ........9-46 9.11.1.17 PCI Inbound Comparison Mask Registers (PICMRx) ......9-47 MOTOROLA Contents For More Information On This Product, Go to: www.freescale.com...
  • Page 16 Outbound Doorbell Register (ODR) ............9-72 9.12.2.2 Inbound Doorbell Register (IDR) ............. 9-73 9.12.3 O Unit ......................9-74 9.12.3.1 PCI Configuration Identification .............. 9-75 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 17 Descriptor in Little-Endian Mode............9-103 9.14 Error Handling ....................9-103 9.14.1 Interrupt and Error Signals ................9-104 9.14.1.1 PCI Bus Error Signals................9-104 9.14.1.1.1 System Error (SERR) ................9-104 MOTOROLA Contents xvii For More Information On This Product, Go to: www.freescale.com...
  • Page 18 11.2.3 Error Checking and Correction (ECC) ............11-9 11.2.4 Parity Generation and Checking ..............11-9 11.2.5 Transfer Error Acknowledge (TEA) Generation ........... 11-9 xviii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 19 Last Data In to Precharge—Write Recovery ........... 11-44 11.4.6.6 Refresh Recovery Interval (RFRC) ............11-44 11.4.6.7 External Address Multiplexing Signal............. 11-45 11.4.6.8 External Address and Command Buffers (BUFCMD)......11-45 MOTOROLA Contents For More Information On This Product, Go to: www.freescale.com...
  • Page 20 Extended Hold Time on Read Accesses ..........11-84 11.6.5 UPM DRAM Configuration Example ............11-84 11.6.6 Differences between the MPC8xx UPM and MPC82xx UPM....11-85 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 21 MPC8280 Restrictions ..................13-7 13.6 Nonscan Chain Operation .................. 13-7 Part IV Communications Processor Module Intended Audience ..................... IV-1 Contents ......................IV-1 Suggested Reading..................... IV-3 MPC82xx Documentation ................. IV-3 MOTOROLA Contents For More Information On This Product, Go to: www.freescale.com...
  • Page 22 RISC Timer Interrupt Handling ..............14-29 14.6.9 RISC Timer Table Scan Algorithm.............. 14-29 14.6.10 Using the RISC Timers to Track CP Loading ..........14-30 xxii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 23 CMX SI2 Clock Route Register (CMXSI2CR)........... 16-12 16.4.4 CMX FCC Clock Route Register (CMXFCR) ..........16-13 16.4.5 CMX SCC Clock Route Register (CMXSCR) ..........16-16 16.4.6 CMX SMC Clock Route Register (CMXSMR) .......... 16-19 MOTOROLA Contents xxiii For More Information On This Product, Go to: www.freescale.com...
  • Page 24 Peripheral to Memory................19-11 19.5.2.1.2 Memory to Peripheral ................19-11 19.5.2.2 Single Address (Fly-By) Transfers ............19-12 19.5.2.2.1 Peripheral-to-Memory Fly-By Transfers ..........19-12 xxiv MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 25 SCC Buffer Descriptors (BDs) ................ 20-11 20.3 SCC Parameter RAM..................20-13 20.3.1 SCC Base Addresses..................20-15 20.3.2 Function Code Registers (RFCR and TFCR) ..........20-15 20.3.3 Handling SCC Interrupts ................20-16 MOTOROLA Contents For More Information On This Product, Go to: www.freescale.com...
  • Page 26 SCC UART Event Register (SCCE) and Mask Register (SCCM) ....21-20 21.20 SCC UART Status Register (SCCS)..............21-22 21.21 SCC UART Programming Example ..............21-23 21.22 S-Records Loader Application................. 21-24 xxvi MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 27 SCC BISYNC DLE Register (BDLE) ............... 23-8 23.9 Sending and Receiving the Synchronization Sequence ........23-9 23.10 Handling Errors in the SCC BISYNC ............... 23-9 23.11 BISYNC Mode Register (PSMR)..............23-10 MOTOROLA Contents xxvii For More Information On This Product, Go to: www.freescale.com...
  • Page 28 25.3 Connecting the MPC8280 to Ethernet ............... 25-4 25.4 SCC Ethernet Channel Frame Transmission ............. 25-5 25.5 SCC Ethernet Channel Frame Reception............25-6 xxviii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 29 USB Function Description................. 27-4 27.4.1 USB Function Controller Transmit/Receive..........27-5 27.5 USB Host Description ..................27-8 27.5.1 USB Host Controller Transmit/Receive ............27-9 27.5.1.1 Packet-Level Interface ................27-10 MOTOROLA Contents xxix For More Information On This Product, Go to: www.freescale.com...
  • Page 30 SMC Function Code Registers (RFCR/TFCR) ......... 28-9 28.2.4 Disabling SMCs On-the-Fly ................28-9 28.2.4.1 SMC Transmitter Full Sequence.............. 28-10 28.2.4.2 SMC Transmitter Shortcut Sequence ............28-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 31 SMC GCI C/I Channel Reception Process ..........28-34 28.5.4 SMC GCI Commands.................. 28-35 28.5.5 SMC GCI Monitor Channel RxBD ............. 28-35 28.5.6 SMC GCI Monitor Channel TxBD.............. 28-36 MOTOROLA Contents xxxi For More Information On This Product, Go to: www.freescale.com...
  • Page 32 Filtering Limitations ................29-28 29.3.4.4.4 Resetting the SU Filtering Mechanism..........29-29 29.3.4.5 Octet Counting Mode—SS7 Mode............29-29 29.4 Channel Extra Parameters................29-29 29.5 Superchannels ....................29-30 xxxii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 33 FCC Function Code Registers (FCRx) ............30-14 30.8 Interrupts from the FCCs ................. 30-15 30.8.1 FCC Event Registers (FCCEx) ..............30-15 30.8.2 FCC Mask Registers (FCCMx) ..............30-15 MOTOROLA Contents xxxiii For More Information On This Product, Go to: www.freescale.com...
  • Page 34 APC Unit Scheduling Mechanism............... 31-10 31.3.3 Determining the Scheduling Table Size............31-11 31.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table....31-11 xxxiv MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 35 User-Defined Cells (UDC) ................31-35 31.7.1 UDC Extended Address Mode (UEAD)............31-35 31.8 ATM Layer Statistics ..................31-36 31.9 ATM-to-TDM Interworking ................31-36 31.9.1 Automatic Data Forwarding ................ 31-37 MOTOROLA Contents xxxv For More Information On This Product, Go to: www.freescale.com...
  • Page 36 31.10.5.2 Receive Buffer Operation ................ 31-70 31.10.5.2.1 Static Buffer Allocation ............... 31-70 31.10.5.2.2 Global Buffer Allocation ..............31-71 31.10.5.2.3 Free Buffer Pools................. 31-72 xxxvi MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 37 FCC Transmit Internal Rate Port Enable Registers (FIRPERx) ....31-99 31.15.1.5 FCC Internal Rate Event Registers (FIRERx) ........31-100 31.15.1.6 FCC Internal Rate Selection Registers (FIRSRx_HI, FIRSRx_LO) ..31-101 MOTOROLA Contents xxxvii For More Information On This Product, Go to: www.freescale.com...
  • Page 38 Receive Connection Table (RCT)..............32-28 32.9.1.1 AAL1 CES Protocol-Specific RCT ............32-30 32.9.2 Transmit Connection Table (TCT)............... 32-33 32.9.2.1 AAL1 CES Protocol-Specific TCT ............32-36 xxxviii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 39 AAL2 RX Data Structures ................33-25 33.4.4.1 AAL2 Protocol-Specific RCT ..............33-25 33.4.4.2 CID Mapping Tables and RxQDs............33-28 33.4.4.3 CPS Rx Queue Descriptors..............33-28 33.4.4.4 CPS Receive Buffer Descriptor (RxBD) ..........33-29 MOTOROLA Contents xxxix For More Information On This Product, Go to: www.freescale.com...
  • Page 40 On-Demand Cell Processing ............... 34-21 34.3.3.2.2 IDCR-Regulated Cell Processing ............34-21 34.3.3.3 Cell Processing Task................34-22 34.4 IMA Programming Model ................34-23 34.4.1 Data Structure Organization ................ 34-23 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 41 IDCR Master Clock ................. 34-50 34.4.8.2 IDCR FCC Parameter Shadow ..............34-50 34.4.8.2.1 MPC8280 Features Unavailable if IDCR is Used ....... 34-50 34.4.8.2.2 Programming the FCC Parameter Shadow.......... 34-51 MOTOROLA Contents For More Information On This Product, Go to: www.freescale.com...
  • Page 42 Rx Steps ....................34-66 34.5.4.5.2 TX Parameters ..................34-67 34.5.4.6 Link Receive Deactivation Procedure ............. 34-68 34.5.4.7 Link Receive Reactivation Procedure ............. 34-68 xlii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 43 Errored Cell Counters 1–8 (TC_ECCx)........... 35-13 35.4.3.4 Corrected Cell Counters 1–8 (TC_CCCx)..........35-13 35.4.3.5 Transmitted IDLE Cell Counters 1–8 (TC_ICCx)........35-13 35.4.3.6 Filtered Cell Counters 1–8 (TC_FCCx)........... 35-13 35.4.4 Programming FCC2..................35-13 MOTOROLA Contents xliii For More Information On This Product, Go to: www.freescale.com...
  • Page 44 FCC Ethernet Mode Register (FPSMR) ............36-21 36.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM) ......36-23 36.19 Ethernet RxBDs ....................36-25 36.20 Ethernet TxBDs ....................36-28 xliv MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 45 SPI Examples with Different SPMODE[LEN] Values......39-9 39.4.2 SPI Event/Mask Registers (SPIE/SPIM) ............. 39-10 39.4.3 SPI Command Register (SPCOM) .............. 39-11 39.5 SPI Parameter RAM ..................39-12 39.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR)......39-13 MOTOROLA Contents For More Information On This Product, Go to: www.freescale.com...
  • Page 46 41.2.3 Port Data Direction Registers (PDIRA–PDIRD)........... 41-3 41.2.4 Port Pin Assignment Register (PPAR)............41-4 41.2.5 Port Special Options Registers A–D (PSORA–PSORD) ......41-4 xlvi MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 47 Register Quick Reference Guide PowerPC Registers—User Registers ..............A-1 PowerPC Registers—Supervisor Registers ............A-2 MPC8280-Specific SPRs ..................A-3 Appendix B Revision History Glossary of Terms and Abbreviations Index MOTOROLA Contents xlvii For More Information On This Product, Go to: www.freescale.com...
  • Page 48 Freescale Semiconductor, Inc. Contents Paragraph Page Number Title Number xlviii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 49 4-11 SIU Interrupt Priority Register (SIPRR) ..............4-19 4-12 CPM High Interrupt Priority Register (SCPRR_H)..........4-20 4-13 CPM Low Interrupt Priority Register (SCPRR_L)........... 4-21 4-14 SIPNR_H ........................4-22 MOTOROLA Figures xlix For More Information On This Product, Go to: www.freescale.com...
  • Page 50 Signal Groupings......................7-2 Single-MPC8280 Bus Mode ..................8-3 60x-Compatible Bus Mode ..................8-4 Basic Transfer Protocol....................8-5 Address Bus Arbitration with External Bus Master............ 8-9 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 51 PCI Error Control Capture Register (PCI_ECCR) ........... 9-44 9-29 PCI Inbound Translation Address Registers (PITARx) ..........9-46 9-30 PCI Inbound Base Address Registers (PIBARx)............9-47 9-31 PCI Inbound Comparison Mask Registers (PICMRx)..........9-48 MOTOROLA Figures For More Information On This Product, Go to: www.freescale.com...
  • Page 52 Outbound Free_FIFO Head Pointer Register (OFHPR) ........... 9-80 9-70 Outbound Free_FIFO Tail Pointer Register (OFTPR)..........9-81 9-71 Outbound Post_FIFO Head Pointer Register (OPHPR) ........... 9-82 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 53 60x Bus-Assigned UPM Refresh Timer (PURT)............ 11-31 11-15 Local Bus-Assigned UPM Refresh Timer (LURT)..........11-31 11-16 60x Bus-Assigned SDRAM Refresh Timer (PSRT) ..........11-32 11-17 Local Bus-Assigned SDRAM Refresh Timer (LSRT)..........11-33 MOTOROLA Figures liii For More Information On This Product, Go to: www.freescale.com...
  • Page 54 RAM Array Indexing ....................11-69 11-57 Memory Refresh Timer Request Block Diagram ........... 11-70 11-58 Memory Controller UPM Clock Scheme for Integer Clock Ratios......11-72 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 55 13-4 Observe-Only Input Pin Cell (I.Obs) ................ 13-4 13-5 Output Control Cell (IO.CTL) .................. 13-5 13-6 General Arrangement of Bidirectional Pin Cells ............13-5 14-1 CPM Block Diagram....................14-3 MOTOROLA Figures For More Information On This Product, Go to: www.freescale.com...
  • Page 56 Bank of Clocks......................16-5 16-4 CMX UTOPIA Address Register (CMXUAR) ............16-7 16-5 Connection of the Master Address................16-9 16-6 Connection of the Slave Address ................16-9 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 57 Output Delay from CTS Asserted for Synchronous Protocols ....... 20-19 20-11 CTS Lost in Synchronous Protocols ............... 20-20 20-12 Using CD to Control Synchronous Protocol Reception.......... 20-21 20-13 DPLL Receiver Block Diagram ................20-22 MOTOROLA Figures lvii For More Information On This Product, Go to: www.freescale.com...
  • Page 58 23-9 SCC Status Registers (SCCS) ................. 23-16 24-1 Sending Transparent Frames Between MPC8280s........... 24-5 24-2 SCC Transparent Receive Buffer Descriptor (RxBD) ..........24-9 lviii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 59 USB Transmit Buffer Descriptor (Tx BD),............. 27-30 27-21 USB Transaction Buffer Descriptor (TrBD), ............27-32 28-1 SMC Block Diagram....................28-2 28-2 SMC Mode Registers (SMCMR1/SMCMR2)............28-3 28-3 SMC Memory Structure.................... 28-6 MOTOROLA Figures For More Information On This Product, Go to: www.freescale.com...
  • Page 60 MCC Transmit Buffer Descriptor (TxBD).............. 29-47 30-1 FCC Block Diagram....................30-3 30-2 General FCC Mode Register (GFMR)..............30-4 30-3 General FCC Expansion Mode Register (GFEMR) ..........30-7 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 61 AAL1 Protocol-Specific RCT................. 31-51 31-29 AAL0 Protocol-Specific RCT................. 31-53 31-30 Transmit Connection Table (TCT) Entry ..............31-54 31-31 AAL5 Protocol-Specific TCT ................. 31-58 31-32 AAL1 Protocol-Specific TCT ................. 31-59 MOTOROLA Figures For More Information On This Product, Go to: www.freescale.com...
  • Page 62 AAL1 Transmit Cell Format ..................32-3 32-2 AAL1 SDT Cell Types....................32-3 32-3 AAL1 Framing Formats.................... 32-4 32-4 AAL1 CES Receiver Data flow ................32-6 lxii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 63 Buffer Structure Example for CPS Packets ............33-15 33-9 CPS TxBD....................... 33-16 33-10 CPS Packet Header Format..................33-17 33-11 SSSAR Tx Queue Descriptor.................. 33-17 33-12 SSSAR TxBD ......................33-19 33-13 CID Mapping Process ..................... 33-23 MOTOROLA Figures lxiii For More Information On This Product, Go to: www.freescale.com...
  • Page 64 IMA Transmit Queue ....................34-46 34-27 Cell Buffer in Delay Compensation Buffer ............34-47 34-28 IMA Delay Compensation Buffer................34-47 34-29 IMA Interrupt Queue Entry..................34-48 lxiv MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 65 38-1 In-Line Synchronization Pattern ................38-3 38-2 Sending Transparent Frames between MPC8280s ........... 38-4 39-1 SPI Block Diagram ....................39-1 39-2 Single-Master/Multi-Slave Configuration ..............39-4 39-3 Multi-Master Configuration..................39-6 MOTOROLA Figures For More Information On This Product, Go to: www.freescale.com...
  • Page 66 Port Pin Assignment Register (PPARA–PPARD)............. 41-4 41-5 Special Options Registers (PSORA–POSRD)............41-5 41-6 Port Functional Operation ..................41-6 41-7 Primary and Secondary Option Programming ............41-8 lxvi MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 67 TESCR2 Field Descriptions..................4-42 4-17 L_TESCR1 Field Descriptions ................. 4-43 4-18 L_TESCR2 Field Descriptions ................. 4-44 4-19 TMCNTSC Field Descriptions ................. 4-45 4-20 TMCNTAL Field Descriptions ................. 4-46 MOTOROLA Tables lxvii For More Information On This Product, Go to: www.freescale.com...
  • Page 68 GPCR Field Descriptions..................9-38 PCI_GCR Field Descriptions..................9-39 9-10 ESR Field Descriptions ..................... 9-40 9-11 EMR Field Descriptions.................... 9-41 9-12 ECR Field Descriptions .................... 9-42 lxviii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 69 IDR Field Descriptions ..................... 9-74 9-50 IFHPR Field Descriptions ..................9-76 9-51 IFTPR Field Descriptions ..................9-77 9-52 IPHPR Field Descriptions ..................9-78 9-53 IPTPR Field Descriptions..................9-79 MOTOROLA Tables lxix For More Information On This Product, Go to: www.freescale.com...
  • Page 70 Local Bus-Assigned UPM Refresh Timer (LURT)..........11-32 11-15 60x Bus-Assigned SDRAM Refresh Timer (PSRT) ..........11-32 11-16 LSRT Field Descriptions..................11-33 11-17 MPTPR Field Descriptions ..................11-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 71 14-7 CP Command Opcodes ................... 14-15 14-8 Command Descriptions................... 14-16 14-9 Buffer Descriptor Format..................14-23 14-10 Parameter RAM ...................... 14-24 14-11 RISC Timer Table Parameter RAM ................ 14-26 MOTOROLA Tables lxxi For More Information On This Product, Go to: www.freescale.com...
  • Page 72 Parallel I/O Register Programming—Port C ............19-31 19-13 Parallel I/O Register Programming—Port A ............19-31 19-14 Parallel I/O Register Programming—Port D ............19-31 lxxii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 73 SCC BISYNC Parameter RAM Memory Map ............23-4 23-2 Transmit Commands ....................23-5 23-3 Receive Commands....................23-5 23-4 Control Character Table and RCCM Field Descriptions .......... 23-7 23-5 BSYNC Field Descriptions ..................23-8 MOTOROLA Tables lxxiii For More Information On This Product, Go to: www.freescale.com...
  • Page 74 RFCR and TFCR Fields ..................27-17 27-9 USMOD Fields ....................... 27-18 27-10 USADR Fields ......................27-19 27-11 USEPx Field Descriptions ..................27-19 27-12 USCOM Fields......................27-21 lxxiv MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 75 29-6 Channel-Specific Parameters for Transparent Operation........29-12 29-7 CHAMR Field Descriptions—Transparent Mode ..........29-14 29-8 CES-Specific Global MCC Parameters ..............29-15 29-9 CHAMR Field Descriptions—CES Mode .............. 29-17 MOTOROLA Tables lxxv For More Information On This Product, Go to: www.freescale.com...
  • Page 76 AAL1 Protocol-Specific RCT Field Descriptions ..........31-52 31-20 AAL0-Specific RCT Field Descriptions..............31-53 31-21 TCT Field Descriptions................... 31-56 31-22 AAL5-Specific TCT Field Descriptions ..............31-58 lxxvi MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 77 32-6 AAL1 CES Protocol-Specific RCT Field Descriptions .......... 32-31 32-7 TCT Field Descriptions................... 32-34 32-8 AAL1 CES Protocol-Specific TCT Field Descriptions .......... 32-36 32-9 OCASSR Field Descriptions................... 32-37 MOTOROLA Tables lxxvii For More Information On This Product, Go to: www.freescale.com...
  • Page 78 34-16 ILTCNTL Field Descriptions .................. 34-40 34-17 ILTSTATE Field Descriptions................. 34-41 34-18 ITINTSTAT Field Descriptions................34-42 34-19 IMA Link Receive Table Entry................34-42 lxxviii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 79 HDLC Transmission Errors ..................37-7 37-5 HDLC Reception Errors ................... 37-7 37-6 FPSMR Field Descriptions ..................37-8 37-7 RxBD field Descriptions ..................37-11 37-8 HDLC TxBD Field Descriptions ................37-13 MOTOROLA Tables lxxix For More Information On This Product, Go to: www.freescale.com...
  • Page 80 User-Level PowerPC Registers (non-SPRs) .............. A-1 User-Level PowerPC SPRs ..................A-1 Supervisor-Level PowerPC Registers ................ A-2 Supervisor-Level PowerPC SPRs ................A-2 MPC8280-Specific Supervisor-Level SPRs .............. A-3 lxxx MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 81: Before Using This Manual-Important Note

    Before Using this Manual—Important Note Before using this manual, determine whether it is the latest revision and if there are errata or addenda. To locate any published errata or updates for this document, refer to the worldwide web at www.motorola.com/semiconductors. MOTOROLA About This Book...

  • Page 82: Audience

    PCI Specification Revision 2.2. — Chapter 10, “Clocks and Power Control,” describes the clocking architecture of the MPC8280. lxxxii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 83 — Chapter 22, “SCC HDLC Mode,” describes the MPC8280 implementation of HDLC protocol. — Chapter 23, “SCC BISYNC Mode,” describes the MPC8280 implementation of byte-oriented BISYNC protocol developed by IBM for use in networking products. MOTOROLA About This Book lxxxiii For More Information On This Product, Go to: www.freescale.com...
  • Page 84 NMSI) ports because of its internally implemented TC-layer functionality. — Chapter 36, “Fast Ethernet Controller,” describes the MPC8280’s implementation of the Ethernet IEEE 802.3 protocol. lxxxiv MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 85: Suggested Reading

    Architecture documentation is organized in the following types of documents: • Manuals—These books provide details about individual implementations of the PowerPC architecture and are intended to be used with the Programming Environments Manual. These include the G2 Core Reference Manual (Motorola order #: G2CORERM). MOTOROLA...

  • Page 86: Conventions

    • Application notes—These short documents contain useful information about specific design issues useful to programmers and engineers working with Motorola’s processors. For a current list of documentation, refer to www.motorola.com/semiconductors. Conventions This document uses the following notational conventions: Bold entries in figures and tables showing registers and parameter Bold RAM should be initialized by the user.

  • Page 87: Acronyms And Abbreviations

    Register used for determining the source of a DSI exception DTLB Data translation lookaside buffer Effective address EEST Enhanced Ethernet serial transceiver EPROM Erasable programmable read-only memory Floating-point register FPSCR Floating-point status and control register MOTOROLA About This Book lxxxvii For More Information On This Product, Go to: www.freescale.com...
  • Page 88 Machine state register Not a number Next instruction address NMSI Nonmultiplexed serial interface No-op No operation Operating environment architecture Open systems interconnection Peripheral component interconnect lxxxviii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 89 Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UIMM Unsigned immediate value UISA User instruction set architecture User-programmable machine MOTOROLA About This Book lxxxix For More Information On This Product, Go to: www.freescale.com...

  • Page 90: Powerpc Architecture Terminology Conventions

    Table iii describes instruction field notation conventions used in this manual. Table iii. Instruction Field Conventions The Architecture Specification Equivalent to: BA, BB, BT crbA, crbB, crbD (respectively) BF, BFA crfD, crfS (respectively) MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 91 Table iii. Instruction Field Conventions (continued) The Architecture Specification Equivalent to: RA, RB, RT, RS rA, rB, rD, rS (respectively) SIMM UIMM /, //, /// 0...0 (shaded) MOTOROLA About This Book For More Information On This Product, Go to: www.freescale.com...
  • Page 92 Freescale Semiconductor, Inc. xcii MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 93: Part I Overview

    Prefix to denote hexadecimal number Prefix to denote binary number rA, rB Instruction syntax used to identify a source GPR Instruction syntax used to identify a destination GPR MOTOROLA Part I. Overview For More Information On This Product, Go to: www.freescale.com...

  • Page 94: Acronyms And Abbreviations

    Fast communications controller Floating-point register GPCM General-purpose chip-select machine General-purpose register HDLC High-level data link control Inter-integrated circuit IEEE Institute of Electrical and Electronics Engineers MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 95 Serial management controller Serial peripheral interface Special-purpose register SRAM Static random access memory Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit MOTOROLA Part I. Overview For More Information On This Product, Go to: www.freescale.com...
  • Page 96 Freescale Semiconductor, Inc. Table I-i. Acronyms and Abbreviated Terms (continued) Term Meaning UART Universal asynchronous receiver/transmitter UISA User instruction set architecture User-programmable machine Virtual environment architecture MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 97: Overview

    — Separate 16-Kbyte data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm — PowerPC architecture-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface MOTOROLA Chapter 1. Overview For More Information On This Product, Go to: www.freescale.com...
  • Page 98 — PCI host bridge or peripheral capabilities — Includes 4 DMA channels for the following transfers: – PCI-to-60x to 60x-to-PCI – 60x-to-PCI to PCI-to-60x MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 99 — Interfaces to G2_LE core through an on-chip 32-Kbyte dual-port data RAM, an on-chip 32-Kbyte dual-port instruction RAM and DMA controller — Serial DMA channels for receive and transmit on all serial channels MOTOROLA Chapter 1. Overview For More Information On This Product,...
  • Page 100 –Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub. –Flexible data buffers with multiple buffers per frame MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 101 – Independent transmit and receive routing, frame synchronization – Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces — Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels —...

  • Page 102: Architecture Overview

    Both the system core and the CPM have an internal PLL, which allows independent optimization of the frequencies at which they run. The system core and CPM are both connected to the 60x bus. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 103 MPC8280 has an internal PCI bridge with an efficient 60x-to-PCI DMA for memory block transfers. • Applications that require both the local bus and PCI bus need to connect an external PCI bridge. MOTOROLA Chapter 1. Overview For More Information On This Product, Go to: www.freescale.com...
  • Page 104 Kbps HDLC or transparent channels, multiplexed on up to eight TDM interfaces. The MCC also supports super-channels of rates higher than 64 Kbps and subchanneling of the 64-Kbps channels. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 105 Although many registers are new, most registers retain the old status and event bits, so an understanding of the programming models of the MC68360, MPC860, or MPC85015 is helpful. Note that the MPC8280 initialization code requires changes from the MPC860 initialization code (Motorola provides reference code). 1.3.1 Signals Figure 1-2 shows MPC8280 signals grouped by function.
  • Page 106 • On-chip crystal oscillators (must use external oscillator) • 4-MHz oscillator (input clock must be at the bus speed) • Low power (stand-by) modes 1-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 107 This does not imply that the device is not fully activated in MOTOROLA Chapter 1. Overview...
  • Page 108 256 * 64 Kbps 45-Mbps HDLC 100 BaseT 256 * 64 Kbps 100 BaseT 16 * 576 Kbps For the MPC8270 see Table 1-3. 1-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 109 • Section 1.7.1.2, “Regional Office Router” • Section 1.7.1.3, “LAN-to-WAN Bridge Router” • Section 1.7.1.4, “Cellular Base Station” • Section 1.7.1.5, “Telecommunications Switch Controller” • Section 1.7.1.6, “SONET Transmission Controller” MOTOROLA Chapter 1. Overview 1-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 110 The local bus can be used as an interface to a bank of DSPs that can run code that performs analog modem signal modulation. Data to and from the DSPs can be transferred through the parallel bus with the internal virtual IDMA. 1-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 111 10/100 BaseT LAN connections. In all the examples, the SCC ports can be used for management. 1.7.1.3 LAN-to-WAN Bridge Router Figure 1-5 shows a LAN-to-WAN router configuration, which is similar to the previous example. MOTOROLA Chapter 1. Overview 1-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 112 60x Bus Channelized Data (up to 256 channels) TDM1 DSP Bank Local Bus Slow Slaves Comm SMC/I2C/SPI/SCC Local Figure 1-6. Cellular Base Station Configuration 1-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 113 The CPM supports a total aggregate throughput of 710 Mbps at 133 MHz. This includes two full-duplex 100 BaseT and one full-duplex 155 Mbps for ATM. The G2_LE core can operate at a different (higher) speed, if the application requires it. MOTOROLA Chapter 1. Overview 1-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 114 • Section 1.7.2.3, “High-Performance System Microprocessor” • Section 1.7.2.4, “PCI” • Section 1.7.2.5, “PCI with 155-Mbps ATM” • Section 1.7.2.6, “The MPC8280 as PCI Agent” 1-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 115 MPC8280 SDRAM/SRAM/DRAM/Flash 60x Bus Communication Channels SDRAM/SRAM/DRAM 155 Mbps Local Bus UTOPIA Connection Tables Figure 1-9. Basic System Configuration MOTOROLA Chapter 1. Overview 1-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 116 MPC8280 in master mode with the core enabled. The core in MPC8280-A can access the memory on the local bus of MPC8280-B. 1-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 117 Connection Tables Figure 1-11. High-Performance System Microprocessor Configuration In this system, the G2_LE core internal is disabled and an external high-performance microprocessor is connected to the 60x bus. MOTOROLA Chapter 1. Overview 1-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 118 MPC8280 can be configured as a host or as an agent on the PCI bus. The 60x bus and PCI bus are asynchronous; there is no frequency dependency between the two. The PCI bus is a 3.3-V bus. 1-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 119 In systems with fewer than 128 active connections or where the ATM average bit rate is lower that 155 Mbps, the local bus may not be necessary to store connection tables, and it may be possible to use it as PCI bus. MOTOROLA Chapter 1. Overview 1-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 120 PCI bus. An external PCI bridge is used to connect the host to the PCI bus. The internal PCI bridge in the MPC8280 is used to bridge between the PCI bus and the 60x bus on the MPC8280. 1-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 121: G2_Le Core

    32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits. Figure 2-1 is a block diagram of the processor core. MOTOROLA Chapter 2. G2_LE Core For More Information On This Product,...
  • Page 122 Clock Interface Multiplier Touch Load Buffer Core Interface Copy-Back Buffer 32-Bit Address Bus 32-/64-Bit Data Bus Figure 2-1. MPC8280 Integrated Processor Core Block Diagram MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 123 This section describes the major features of the processor core: • High-performance, superscalar microprocessor — As many as three instructions issued and retired per clock cycle MOTOROLA Chapter 2. G2_LE Core For More Information On This Product, Go to: www.freescale.com...
  • Page 124 — Eight-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks — Software table search operations and updates supported through fast trap mechanism MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 125 The BPU folds out branch instructions for unconditional branches or conditional branches unaffected by instructions in progress in the execution pipeline. MOTOROLA Chapter 2. G2_LE Core For More Information On This Product,...
  • Page 126 CTR can be copied to or from any GPR. Because the BPU uses dedicated registers rather than GPRs or FPRs, execution of branch instructions is largely independent from execution of other instructions. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 127 Load and store instructions are issued and translated in program order; however, the actual memory accesses can occur out of order. Synchronizing instructions are provided to enforce strict ordering where needed. MOTOROLA Chapter 2. G2_LE Core For More Information On This Product,...
  • Page 128 The memory subsystem support functions are described in the following subsections. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 129 (OEA), as well as the G2_LE core implementation-specific registers. Full descriptions of the basic register set defined by the PowerPC architecture are provided in Chapter 2 in The Programming Environments Manual. MOTOROLA Chapter 2. G2_LE Core For More Information On This Product,...
  • Page 130 G2 Core Reference Manual, is determined by the CIP bit in the hard reset configuration word in the MPC8280. This is described in Section 5.4.1, “Hard Reset Configuration Word.” 2-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 131 DABR SPR 1013 DABR2 SPR 317 These implementation-specific registers may not be supported by other PowerPC processors or processor cores. Figure 2-2. MPC8280 Programming Model—Registers MOTOROLA Chapter 2. G2_LE Core 2-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 132 Note that the machine check exception is further affected by MSR[ME], which specifies whether the processor checkstops or continues processing. — Reserved 2-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 133 For those transactions, however, CI reflects the original state determined by address translation regardless of cache disabled status. ICE is zero at power-up. 1 The instruction cache is enabled MOTOROLA Chapter 2. G2_LE Core 2-13 For More Information On This Product,...
  • Page 134 0 M bit not reflected on 60x bus. Instruction fetches are treated as nonglobal on the bus. 1 Instruction fetches reflect the M bit from the WIM settings on the 60x bus. 2-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 135 The processor core implements an additional hardware implementation-dependent register, shown in Figure 2-5. 18 19 23 24 26 27 — HBE — IWLCK — DWLCK — Figure 2-5. Hardware Implementation-Dependent Register 2 (HID2) MOTOROLA Chapter 2. G2_LE Core 2-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 136 These simple addressing modes allow efficient address generation for memory accesses. Calculation of the effective address for aligned transfers occurs in a single clock cycle. 2-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 137 — Branch and trap — Condition register logical — Primitives used to construct atomic memory operations (lwarx and stwcx.) MOTOROLA Chapter 2. G2_LE Core 2-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 138 Processors that implement the PowerPC architecture follow the program flow when they are in the normal execution state. However, the flow of instructions can be interrupted 2-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 139 Implementation As shown in Figure 2-1, the caches provide a 64-bit interface to the instruction fetch unit and load/store unit. The surrounding logic selects, organizes, and forwards the requested MOTOROLA Chapter 2. G2_LE Core 2-19 For More Information On This Product,...
  • Page 140 Because the processor core data cache tags are single-ported, simultaneous load or store and snoop accesses cause resource contention. Snoop accesses have the highest priority and 2-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 141 The processor core supports instruction fetching from other instruction cache lines following the forwarding of the critical first double word of a cache line load operation. The processor core’s instruction cache is blocked only until the critical load completes (hits MOTOROLA Chapter 2. G2_LE Core 2-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 142 Unlocked ways of the cache behave normally. Exception Model This section describes the PowerPC exception model and implementation-specific details of the MPC8280 core. 2-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 143 Once the exception is processed, execution resumes at the address of the faulting instruction (or at an alternate address provided by the exception handler). MOTOROLA Chapter 2. G2_LE Core 2-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 144 Table 2-4 define categories of exceptions that the processor core handles uniquely. Note that Table 2-4 includes no synchronous imprecise instructions. 2-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 145 The processor core differs from MPC603e User’s Manual in that it initiates an alignment exception when it detects a misaligned eciwx or ecowx instruction and does not initiate an alignment exception when a little-endian access is misaligned. MOTOROLA Chapter 2. G2_LE Core 2-25 For More Information On This Product, Go to: www.freescale.com...
  • Page 146 01400 A system management interrupt is caused when MSR[EE] = 1 and the SMI input management signal is asserted. interrupt Reserved 01500–02FFF — 2-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 147 Software is responsible for maintaining the consistency of the TLB with memory. The core TLBs are 64-entry, two-way set-associative caches that contain instruction and data address translations. The core provides hardware MOTOROLA Chapter 2. G2_LE Core 2-27 For More Information On This Product, Go to: www.freescale.com...
  • Page 148 • In the execute pipeline stage, each execution unit with an executable instruction executes the selected instruction (perhaps over multiple cycles), writes the 2-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 149 Any software designed around an MPC603e is functional when replaced with the G2_LE except for the specific customer-visible changes listed in Table 2-6. MOTOROLA Chapter 2. G2_LE Core 2-29 For More Information On This Product, Go to: www.freescale.com...
  • Page 150 Setting HID0[ABE] enables the new broadcast feature (new in the dcbst onto the 60x bus PID7v-603e). The default is to not broadcast these operations. 2-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 151 Addition of speed-for-power functionality The processor core implements an additional dynamic power manage- ment mechanism. HID2[SFP] controls this function. See Section 2.3.1.2.3, “Hardware Implementation-Dependent Register 2 (HID2).” MOTOROLA Chapter 2. G2_LE Core 2-31 For More Information On This Product, Go to: www.freescale.com...
  • Page 152 Freescale Semiconductor, Inc. Differences Between the MPC8280 G2_LE Embedded Core and the MPC603e 2-32 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 153 2 The right vertical column is for illustration only. For a complete list of modules and registers, refer to Table 3-1. Figure 3-1. Internal Memory MOTOROLA Chapter 3. Memory Map For More Information On This Product, Go to: www.freescale.com...
  • Page 154 0x10048 Local bus transfer error status control register 1 32 bits 0x0000_0000 4.3.2.12/-43 (L_TESCR1) 0x1004C Local bus transfer error status control register 2 32 bits 0x0000_0000 4.3.2.13/-44 (L_TESCR2) MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 155 0x10158 Base register bank 11 (BR11) 32 bits 0x0000_0000 11.3.1/-14 0x1015C Option register bank 11 (OR11) 32 bits undefined 11.3.2/-16 0x10160 Reserved — 8 bytes — — MOTOROLA Chapter 3. Memory Map For More Information On This Product, Go to: www.freescale.com...
  • Page 156 — 0x10 21F 0x10220 Time counter status and control register (TMCNTSC) 16 bits 0x0000 4.3.2.14/-45 0x10224 Time counter register (TMCNT) 32 bits 0x0000_0000 4.3.2.15/-45 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 157 0x104D8 Outbound post_FIFO tail pointer register (OPTPR) 32 bits 0x0000_0000 9.12.3.3.2/-81 0x104E4 Message unit control register (MUCR) 32 bits 0x0000_0002 9.12.3.4.7/-88 0x104F0 Queue base address register (QBAR) 32 bits 0x0000_0000 9.12.3.4.8/-89 MOTOROLA Chapter 3. Memory Map For More Information On This Product, Go to: www.freescale.com...
  • Page 158 0x10800 PCI outbound translation address register 0 (POTAR0) R/W 32 bits 0x0000_0000 9.11.1.3/-33 0x10808 PCI outbound base address register 0 (POBAR0) 32 bits 0x0000_0000 9.11.1.4/-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 159 0x10C0C SIU interrupt pending register (low) (SIPNR_L) 32 bits 0x0000_0000 4.3.1.4/-22 0x10C10 SIU interrupt priority register (SIPRR) 32 bits 0x0530_9770 4.3.1.2/-19 0x10C14 CPM interrupt priority register (high) (SCPRR_H) 32 bits 0x0530_9770 4.3.1.3/-20 MOTOROLA Chapter 3. Memory Map For More Information On This Product, Go to: www.freescale.com...
  • Page 160 32 bits 0x0000_0000 41.2.5/-4 0x10D4C Port C open drain register (PODRC) 32 bits 0x0000_0000 41.2.1/-2 0x10D50 Port C data register (PDATC) 32 bits 0x0000_0000 41.2.2/-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 161 0x10DB0 Timer 1 event register (TER1) 16 bits 0x0000 18.2.7/-8 0x10DB2 Timer 2 event register (TER2) 16 bits 0x0000 18.2.7/-8 0x10DB4 Timer 3 event register (TER3) 16 bits 0x0000 18.2.7/-8 MOTOROLA Chapter 3. Memory Map For More Information On This Product, Go to: www.freescale.com...
  • Page 162 0x11300 FCC1 general mode register (GFMR1) 32 bits 0x0000_0000 30.2/-3 0x11304 FCC1 protocol-specific mode register (FPSMR1) 32 bits 0x0000_0000 31.13.2/-91 (ATM) 34.4.2.1.1/-24 (IMA) 36.18.1/-21 (Ethernet) 37.6/-8 (HDLC) 3-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 163 0x11328 FCC2 transmit on-demand register (FTODR2) 16 bits 0x0000 30.5/-9 0x1132A Reserved — 16 bits — — 0x1132C FCC2 data synchronization register (FDSR2) 16 bits 0x7E7E 30.4/-8 MOTOROLA Chapter 3. Memory Map 3-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 164 0x1134A Reserved — 16 bits — — 0x1134C FCC3 data synchronization register (FDSR3) 16 bits 0x7E7E 30.4/-8 0x1134E Reserved — 16 bits — — 3-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 165 31 bytes — — 0x113CF FCC3 Extended Registers 0x113D0 General FCC3 expansion mode register (GFEMR3) 8 bits 0x00 30.2.1/-7 0x113D1 Reserved — 47 bytes — — MOTOROLA Chapter 3. Memory Map 3-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 166 16 bits 0x0000 35.4.1.4/-11 0x1144A TC3 filtered cells counter (TC_FCC3) 16 bits 0x0000 35.4.3.6/-13 0x1144C TC3 corrected cells counter (TC_CCC3) 16 bits 0x0000 35.4.3.4/-13 3-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 167 16 bits 0x0000 35.4.1.1/-8 0x114A2 TC6 cell delineation state machine register (CDSMR6) 16 bits 0x0000 35.4.1.2/-9 0x114A4 TC6 event register (TCER6) 16 bits 0x0000 35.4.1.3/-10 MOTOROLA Chapter 3. Memory Map 3-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 168 0x114F0 TC8 transmitted cells counter (TC_TCC8) 16 bits 0x0000 35.4.3.2/-13 0x114F2 TC8 error cells counter (TC_ECC8) 16 bits 0x0000 35.4.3.3/-13 0x114F4 Reserved — 12 bytes — — 3-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 169 0x119DA CP timers mask register (RTMR) 16 bits 0x0000_0000 0x119DC CP time-stamp timer control register (RTSCR) — 16 bits 0x0000 14.3.8/-10 0x119DE Reserved 16 bits — MOTOROLA Chapter 3. Memory Map 3-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 170 0x11A16 Reserved — 8 bits — — 0x11A17 SCC1 status register (SCCS1) 8 bits 0x00 21.20/-22 (UART) 22.12/-15 (HDLC) 23.15/-16 (BISYNC) 24.13/-13 (Transparent) 3-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 171 8 bytes — — 0x11A3F SCC3 0x11A40 SCC3 general mode register (GSMR_L3) 32 bits 0x0000_0000 20.1.1/-3 0x11A44 SCC3 general mode register (GSMR_H3) 32 bits 0x0000_0000 MOTOROLA Chapter 3. Memory Map 3-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 172 — — 0x11A5F SCC4 0x11A60 SCC4 general mode register (GSMR_L4) 32 bits 0x0000_0000 20.1.1/-3 0x11A64 SCC4 general mode register (GSMR_H4) 32 bits 0x0000_0000 3-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 173 0x11A87 Reserved — 24 bits — 28.4.10/-31 (Transparent) 0x11A8A SMC1 mask register (SMCM1) 8 bits 0x00 28.5.9/-37 (GCI) 0x11A8B– Reserved — 7 bytes — — 0x11A91 MOTOROLA Chapter 3. Memory Map 3-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 174 — — 0x11B0E CPM mux UTOPIA address register (CMXUAR) 16 bits 0x0000 16.4.1/-7 0x11B10– Reserved — 16 bytes — — 0x11B1F SI1 Registers 3-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 175 0x11B4C SI2 status register (SI2STR) 8 bits 0x00 15.5.5/-26 0x11B4D Reserved — 16 bits — — 0x11B4E SI2 RAM shadow address register (SI2RSR) 16 bits 0x0000 15.5.3/-24 MCC2 Registers MOTOROLA Chapter 3. Memory Map 3-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 176 0x12600– Reserved — 512 bytes — — 0x127FF SI2 RAM 0x12800– SI 2 transmit routing RAM (SI2TxRAM) R/W 512 bytes undefined 15.4.3/-10 0x129FF 3-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 177 CPM Dual-Port RAM (Instruction) 0x20000– CPM Instruction RAM (IRAM) R/W 32 Kbytes Undefined 0x27FFF MPC8280 only. Reserved on other devices. Reserved on the MPC8270. MOTOROLA Chapter 3. Memory Map 3-25 For More Information On This Product, Go to: www.freescale.com...
  • Page 178 Freescale Semiconductor, Inc. 3-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 179 60x bus configuration. • Chapter 5, “Reset,” describes the behavior of the MPC8280 at reset and start-up. Suggested Reading Supporting documentation for the MPC8280 can be accessed through the world-wide web www.motorola.com/semiconductors. This documentation includes technical specifications, reference materials, and detailed applications notes.
  • Page 180 IEEE Institute of Electrical and Electronics Engineers Least-significant byte Least-significant bit Load/store unit Most-significant byte Most-significant bit Machine state register Peripheral component interconnect II-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 181 Freescale Semiconductor, Inc. Table II-i. Acronyms and Abbreviated Terms (continued) Term Meaning RTOS Real-time operating system Receive Special-purpose register Software watchdog timer Transmit MOTOROLA Part II. Configuration and Reset II-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 182 Freescale Semiconductor, Inc. II-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 183: System Interface Unit (Siu)

    • Power management • 60x bus interface • Flexible, high-performance memory controller • Level-two cache controller interface • PCI interface • IEEE 1149.1 test-access port (TAP) MOTOROLA Chapter 4. System Interface Unit (SIU) For More Information On This Product, Go to: www.freescale.com...
  • Page 184 In addition, it is designed to provide maximum system safeguards against hardware and/or software faults. Table 4-1 describes functions provided in the system configuration and protection submodule. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 185 Figure 4-2. System Configuration and Protection Logic Many aspects of system configuration are controlled by several SIU module configuration registers, described in Section 4.3.2, “System Configuration and Protection Registers.” MOTOROLA Chapter 4. System Interface Unit (SIU) For More Information On This Product,...
  • Page 186 PIT Divide by 512 Ports Programming CPM clock timersclk for TMCNT PC[27] BRG1 PC[29] TMCNTSC[TCF] Ports Programming PC[25] Figure 4-3. Timers Clock Generation MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 187 When a new value is loaded into the PITC, the PIT is updated, the divider is reset, and the counter begins counting. MOTOROLA Chapter 4. System Interface Unit (SIU) For More Information On This Product,...
  • Page 188 The service sequence clears the watchdog timer and the timing process begins again. If a value other than 0x556C or 0xAA39 is written to the SWSR, the entire sequence must start MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 189 Logic Clock Divide By Reload 2,048 Clock Disable 16-Bit SWR/Decrementer Rollover = 0 Reset Time-out or MCP Figure 4-7. Software Watchdog Timer Block Diagram MOTOROLA Chapter 4. System Interface Unit (SIU) For More Information On This Product, Go to: www.freescale.com...
  • Page 190 PIT or TMCNT, from the CPM, the PCI bridge (with its own interrupt controller), and from external pins (port C parallel I/O pins). MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 191 The external IRQ0 can generate MCP as well. Note that the core takes the machine check interrupt when MCP is asserted; it takes an external interrupt for any other interrupt asserted by the interrupt controller. MOTOROLA Chapter 4. System Interface Unit (SIU) For More Information On This Product,...
  • Page 192 The interrupt controller allows masking of each interrupt source. Multiple events within a CPM sub-block event are also maskable. 4-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 193 No (TMCNT,PIT,PCI = Yes) XSIU3 (Spread) No (TMCNT,PIT,PCI = Yes) YCC1 (Grouped) YCC2 (Grouped) YCC3 (Grouped) YCC4 (Grouped) YCC5 (Grouped) YCC6 (Grouped) YCC7 (Grouped) MOTOROLA Chapter 4. System Interface Unit (SIU) 4-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 194 IRQ6 IDMA3 IRQ7 Timer 3 XSIU6 (GSIU = 1) No (TMCNT,PIT,PCI = Yes) YCC5 (Spread) Parallel I/O–PC7 Parallel I/O–PC6 Parallel I/O–PC5 Timer 4 4-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 195 In addition, the grouping of the locations of the YCC entries has the following two options • Group. In the group scheme, all SCCs are grouped together at the top of the priority table, ahead of most other CPM interrupt sources. This scheme is ideal for MOTOROLA Chapter 4. System Interface Unit (SIU) 4-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 196 Table 4-2 shows which interrupt sources have multiple interrupting events. Figure 4-9 shows an example of how the masking occurs, using an SCC as an example. 4-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 197 Table 4-3. Encoding the Interrupt Vector Interrupt Number Interrupt Source Description Interrupt Vector Error (No interrupt) 0b00_0000 0b00_0001 0b00_0010 RISC Timers 0b00_0011 SMC1 0b00_0100 SMC2 0b00_0101 MOTOROLA Chapter 4. System Interface Unit (SIU) 4-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 198 0b10_0000 FCC2 0b10_0001 FCC3 0b10_0010 Reserved 0b10_0011 MCC1 0b10_0100 MCC2 0b10_0101 Reserved 0b10_0110 Reserved 0b10_0111 SCC1 0b10_1000 SCC2 0b10_1001 SCC3 0b10_1010 SCC4 0b10_1011 4-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 199 Requests can be masked independently in the interrupt mask register (SIMR). Notice that the global SIMR is cleared on system reset so pins left floating do not cause false interrupts. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 200 Table 4-2. Field — — GSIU SPS Reset 0000_0000_0000_0000 Addr 0x10C00 Figure 4-10. SIU Interrupt Configuration Register (SICR) 4-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 201 XS4P — Reset 0000 Addr 0x10C10 Field XS5P XS6P XS7P XS8P — Reset 0000 Addr 0x10C12 Figure 4-11. SIU Interrupt Priority Register (SIPRR) MOTOROLA Chapter 4. System Interface Unit (SIU) 4-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 202 — Reset 0000 Addr 0x10C14 Field XC5P XC6P XC7P XC8P — Reset 0000 Addr 0x10C16 Figure 4-12. CPM High Interrupt Priority Register (SCPRR_H) 4-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 203 — Reset 0000 Addr 0x10C18 Field YC5P YC6P YC7P YC8P — Reset 0000 Addr 0x10C20 Figure 4-13. CPM Low Interrupt Priority Register (SCPRR_L) MOTOROLA Chapter 4. System Interface Unit (SIU) 4-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 204 Undefined (the user should write 1s to clear these bits before using) Addr 0x10C10 These fields are zero after reset because their corresponding mask register bits are cleared (disabled). Figure 4-14. SIPNR_H 4-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 205 If the user sets the SIMR bit later, a previously pending interrupt request is processed by the core, according to its assigned priority. The SIMR can be read by the user at any time. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 206 Thus, the user should always include an error vector routine, even if it contains only an rfi instruction. The error vector cannot be masked. 4-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 207 256 instructions. The interrupt code is defined such that its two lsbs are zeroes, allowing indexing into the table, as shown in Figure 4-19. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-25 For More Information On This Product, Go to: www.freescale.com...
  • Page 208 Figure 4-20, determines whether the corresponding port C line asserts an interrupt request upon either a high-to-low change or any change on the pin. External interrupts can come from port C (PC[0-15]). 4-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 209 Bus Configuration Register (BCR) The bus configuration register (BCR), shown in Figure 4-21, contains configuration bits for various features and wait states on the 60x bus. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-27 For More Information On This Product,...
  • Page 210 1 The memory controller asserts CS on the cycle following the assertion of TS by external master accessing an address space controlled by the memory controller. 4-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 211 0 The bus master connected to the arbitration lines is a MPC8280. 1 The bus master connected to the arbitration lines is not a MPC8280. 19–20 — Reserved, should be cleared. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-29 For More Information On This Product, Go to: www.freescale.com...
  • Page 212 EARB PRKM Reset See note 0010 Addr 0x10028 Depends on reset configuration sequence. See Section 5.4.1, “Hard Reset Configuration Word.” Figure 4-22. PPC_ACR 4-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 213 MPC8280 bus masters. Priority field 0 has highest-priority. For information about MPC8280 bus master indexes, see the description of PPC_ACR[PRKM] in Table 4-10. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-31 For More Information On This Product,...
  • Page 214 The local bus arbiter configuration register (LCL_ACR), shown in Figure 4-25, defines the arbiter modes and the parked master on the local bus. Field — DBGD — PRKM Reset 0000_0010 Addr 0x10034 Figure 4-25. LCL_ACR 4-32 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 215 Field Priority Field 4 Priority Field 5 Priority Field 6 Priority Field 7 Reset 0011 0100 0101 0111 Addr 0x10040 Figure 4-26. LCL_ALRH MOTOROLA Chapter 4. System Interface Unit (SIU) 4-33 For More Information On This Product, Go to: www.freescale.com...
  • Page 216 Addr 0x10002 Depends on rest configuration sequence. See Section 5.4.1, “Hard Reset Configuration Word.” Figure 4-28. SIU Model Configuration Register (SIUMCR) 4-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 217 00 Local bus pins function as local bus 01 Local bus pins function as PCI bus. Reserved on all other devices. 10 Local bus pins function as core pins 11 Reserved MOTOROLA Chapter 4. System Interface Unit (SIU) 4-35 For More Information On This Product,...
  • Page 218 1 Parity byte select is enabled. LGPL4 pin is used as local bus parity byte select output from the MPC8280. — Reserved, should be cleared. 4-36 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 219 Depends on reset configuration sequence. See Section 5.4.1, “Hard Reset Configuration Word.” Addr 0x101A8 Field PARTNUM MASKNUM Reset 0000_1010 0000_0000 Addr 0x101AA Figure 4-29. Internal Memory Map Register (IMMR) MOTOROLA Chapter 4. System Interface Unit (SIU) 4-37 For More Information On This Product, Go to: www.freescale.com...
  • Page 220 Reset 1111_1111_1111_1111 Addr 0x10004 Field PBME LBME — SWE SWRI SWP Reset 1111_1111 00_0 Addr 0x10006 Figure 4-30. System Protection Control Register (SYPCR) 4-38 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 221 To prevent software watchdog timer time-out, the user should write 0x556C followed by 0xAA39 to this register, which resides at 0x1000E. SWSR can be written at any time, but returns all zeros when read. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-39 For More Information On This Product, Go to: www.freescale.com...
  • Page 222 Note that this alone does not cause TEA assertion. Usually, in this case, the bus monitor will time-out. 4-40 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 223 The user can set a lower threshold to the number of tolerated single ECC errors by writing some value to ECNT. The counter starts from this value instead of zero. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-41 For More Information On This Product, Go to: www.freescale.com...
  • Page 224 60x bus memory controller bank that had an error. Note that this field is invalid if the error was not caused by ECC or parity checks. 28–31 — Reserved, should be cleared. 4-42 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 225 11–15 Transfer type. Indicates the transfer type of the local bus transaction that caused the TEA. Section 8.4.3.1, “Transfer Type Signal (TT[0–4]) Encoding,” describes the various transfer types. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-43 For More Information On This Product,...
  • Page 226 Note that BNK is invalid if the error was not caused by ECC or PARITY checks. 28–31 — Reserved, should be cleared. 4-44 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 227 The time counter register (TMCNT), shown in Figure 4-36, contains the current value of the time counter. The counter is reset to zero on PORESET reset or hard reset but is not effected by soft reset. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-45 For More Information On This Product, Go to: www.freescale.com...
  • Page 228 0–31 ALARM The alarm interrupt is generated when ALARM field matches the corresponding TMCNT bits. The resolution of the alarm is 1 second. 4-46 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 229 When the counter is enabled, it continues counting using the previous value. 0 Disable counter. 1 Enable counter MOTOROLA Chapter 4. System Interface Unit (SIU) 4-47 For More Information On This Product, Go to: www.freescale.com...
  • Page 230 PITC Periodic interrupt timing count. Bits 0–15 are defined as the PITC, which contains the count for the periodic timer. Setting PITC to 0xFFFF selects the maximum count period. 16–31 — Reserved, should be cleared. 4-48 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 231 Two pairs of registers detect accesses from the 60x bus side to the PCI bridge (other than PCI internal registers accesses). Each pair consists of a PCI base register (PCIBRx) for comparing addresses and a corresponding PCI mask register (PCIMSKx). MOTOROLA Chapter 4. System Interface Unit (SIU) 4-49 For More Information On This Product, Go to: www.freescale.com...
  • Page 232 Valid bit. Indicates that the contents of the PCIBRx and PCIMSKx pairs are valid. 0 This pair is invalid 1 This pair is valid 4-50 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 233 Some functions share pins. The actual pinout of the MPC8280 is shown in the hardware specifications. The control of the actual functionality used on a specific pin is shown in Table 4-26. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-51 For More Information On This Product, Go to: www.freescale.com...
  • Page 234 Controlled dynamically according to the specific memory controller PSDA10/PGPL0 machine that handles the current bus transaction. PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LBS[0–3]/LSDDQM[0–3]/LWE[0–3] LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LSDRAS/LOE LGPL3/LSDCAS LPBS/LGPL4/LUPMWAIT/LGTA LGPL5/LSDAMUX 4-52 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 235 The enabled checkstop event then generates an internal hard reset sequence. JTAG reset When JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated. MOTOROLA Chapter 5. Reset For More Information On This Product,...
  • Page 236 (MODCK[4–7]) taken from the reset configuration word. The main PLL lock can take up to 200 µs depending on the specific chip. During this time HRESET and SRESET are MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 237 The SRESET flow may be initiated externally by asserting SRESET or internally when the chip detects a cause to assert SRESET. In both cases the chip asserts SRESET for 512 input MOTOROLA Chapter 5. Reset For More Information On This Product,...
  • Page 238 1 to it (writing zero has no effect). 0 No software watchdog reset event occurred 1 A software watchdog reset event has occurred MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 239 The reset mode register (RMR), shown in Figure 5-3, is memory-mapped into the SIU register map. Field — Reset 0000_0000_0000_0000 Addr 0x10C94 Field — CSRE Reset 0000_0000_0000_0000 Addr 0x10C96 Figure 5-3. Reset Mode Register (RMR) MOTOROLA Chapter 5. Reset For More Information On This Product, Go to: www.freescale.com...
  • Page 240 RSTCONF inputs of other chips should be connected to the high-order address bits of the configuration master, as described in Table 5-5. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 241 D[0–31] and toggles its A0 address line. Each configuration slave uses its RSTCONF input as a strobe for latching the configuration word during HRESET assertion time. Thus, the first configuration slave whose RSTCONF input is connected to MOTOROLA Chapter 5. Reset For More Information On This Product,...
  • Page 242 Boot port size. Defines the initial value of BR0[PS], the port size for memory controller bank 0. 00 64-bit port size 01 8-bit port size 10 16-bit port size 11 32-bit port size See Section 11.3.1, “Base Registers (BRx).” MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 243 10 Local bus pins function as core pins 11 Reserved 22–23 APPC Address parity pin configuration. Defines the initial value of SIUMCR[APPC]. See Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR).” MOTOROLA Chapter 5. Reset For More Information On This Product, Go to: www.freescale.com...
  • Page 244 EPROM; it is assumed that the default configuration is used upon exiting hard reset. PORESET Configuration Slave Chip HRESET A[0–31] D[0–31] PORESET RSTCONF Figure 5-5. Single Chip with Default Configuration 5-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 245 GND. The RSTCONF inputs of the other MPC8280 devices are tied to the address bus lines, thus assigning them as configuration slaves. See Figure 5-7. MOTOROLA Chapter 5. Reset 5-11 For More Information On This Product,...
  • Page 246 RSTCONF. As Figure 5-7 shows, this complex configuration is done without additional 5-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 247 For 1,024 clocks after PORESET negation, the external hardware can configure the different devices by driving appropriate configuration words on the data bus and asserting RSTCONF for each device to strobe the data being received. MOTOROLA Chapter 5. Reset 5-13 For More Information On This Product,...
  • Page 248 Freescale Semiconductor, Inc. Reset Configuration 5-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 249 • Chapter 13, “IEEE 1149.1 Test Access Port,” describes the dedicated user-accessible test access port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. MOTOROLA Part III. The Hardware Interface III-1 For More Information On This Product,...
  • Page 250 This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC82xx Documentation Supporting documentation for the MPC8280 can be accessed through the world-wide web www.motorola.com/semiconductors. This documentation includes technical specifications, reference materials, and detailed applications notes.

  • Page 251: Communications Processor Module (Cpm)

    Joint Test Action Group LIFO Last-in-first-out Least recently used Least-significant byte Least-significant bit Load/store unit Multiply accumulate Memory management unit Most-significant byte Most-significant bit Machine state register MOTOROLA Part III. The Hardware Interface III-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 252 Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UISA User instruction set architecture User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter III-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 253 Signals that are not active low, such as TSIZ[0–1] (transfer size signals) are referred to as asserted when they are high and negated when they are low. MOTOROLA Chapter 6. External Signals For More Information On This Product,...
  • Page 254 The MPC8280 system bus, shown in Table 6-1, consists of all the signals that interface with the external bus. Many of these pins perform different functions, depending on how the user assigns them. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 255 As an output the MPC8280 asserts this pin to grant 60x data bus ownership to an external bus master. As an input the external arbiter should assert this pin to grant 60x data bus ownership to the MPC8280. MOTOROLA Chapter 6. External Signals For More Information On This Product,...
  • Page 256 The core resumes instructions execution once this pin is negated. EXT_DBG2 External data bus grant 2—(Output) The MPC8280 asserts this pin to grant 60x data bus ownership to an external bus master. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 257 Cache set entry 1—The cache set entry outputs from the core represent the cache replacement set element for the current core transaction reloading into or writing out of the cache. MOTOROLA Chapter 6. External Signals For More Information On This Product,...
  • Page 258 Interrupt request 3—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 259 Section 11.2.14, “BADDR[27:31] Signal Connections.” Address latch enable—This output pin controls the external address latch that should be used in external master 60x bus configuration. MOTOROLA Chapter 6. External Signals For More Information On This Product, Go to: www.freescale.com...
  • Page 260 60x bus parity byte select—In systems in which data parity is stored in a separate chip, this output is used as the byte-select for that chip. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 261 UPM. The values and timing of this pin is programmed in the UPM. PCI_MODCK_H2 PCI MODCK_H2—In PCI mode, defines the operating mode of internal clock circuits. MOTOROLA Chapter 6. External Signals For More Information On This Product, Go to: www.freescale.com...
  • Page 262 PCI interface is the target of a PCI transfer. Assertion of this pin indicates that the PCI target is ready to send or accept a data beat. 6-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 263 PCI bus. When an external PCI arbiter is used, this is an output pin. In this mode assertion of this pin indicates that the MPC8280’s PCI interface is requesting the PCI bus. MOTOROLA Chapter 6. External Signals...
  • Page 264 MPC8280’s internal PCI arbiter is not used, this pin is used for the Hot Swap interface to connect to the host as the enumeration request. 6-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 265 Non-maskable interrupt output—This is an output driven from MPC8280’s internal interrupt controller. Assertion of this output indicates that a non-maskable interrupt is pending in MPC8280’s internal interrupt controller. MOTOROLA Chapter 6. External Signals 6-13 For More Information On This Product,...
  • Page 266 Bank Select 0—The bank select outputs are used for selecting SDRAM bank when the MPC8280 is in 60x compatible bus mode. BNKSEL0 is msb of the three BNKSEL signals. 6-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 267 VCCSYN—This is the power supply of the PLL circuitry. GNDSYN—This is a special ground of the PLL circuitry. VCCSYN1—This is the power supply of the core’s PLL circuitry. MOTOROLA Chapter 6. External Signals 6-15 For More Information On This Product,...
  • Page 268 Freescale Semiconductor, Inc. Signal Descriptions 6-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 269: 60X Signals

    • Data arbitration signals—The MPC8280, in external arbiter mode, uses these signals to arbitrate for data bus mastership. The MPC8280 arbiter uses these signals to enable an external device to arbitrate for data bus mastership. MOTOROLA Chapter 7. 60x Signals For More Information On This Product,...
  • Page 270 Global (GBL) Attributes Cache Inhibit (CI) Write-Through (WT) Address Acknowledge (AACK) Reservation Address Processor Address Retry (ARTRY) TLBISYNC Termination State Figure 7-1. Signal Groupings MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 271 ARTRY and requires a snoop copyback; may also be negated if MPC8280 cancels the bus request internally before receiving a qualified BG. High Impedance—Occurs during a hard reset or checkstop condition MOTOROLA Chapter 7. 60x Signals For More Information On This Product, Go to: www.freescale.com...
  • Page 272 Timing Comments Assertion—May occur on any cycle. Once the MPC8280 has assumed address bus ownership, it does not begin checking for BG again until the cycle after AACK. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 273 Negated—Indicates that MPC8280 is not the current address bus master. Timing Comments Assertion—Occurs the cycle after a qualified BG is accepted by MPC8280 and remains asserted for the duration of the address tenure. MOTOROLA Chapter 7. 60x Signals For More Information On This Product, Go to: www.freescale.com...
  • Page 274 Assertion is coincident with the first clock that ABB is asserted. High Impedance—Occurs the cycle following the assertion of AACK (same cycle as ABB negation). MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 275 Negated—Has no special meaning. Timing Comments Assertion/Negation—Must be valid on the same cycle that TS is asserted; sampled by the processor only on this cycle. MOTOROLA Chapter 7. 60x Signals For More Information On This Product, Go to: www.freescale.com...
  • Page 276 Size of Transfer”). During graphics transfer operations, these signals form part of the Resource ID (see TBST). Timing Comments Assertion/Negation—Same as A[0–31]. High Impedance—Same as A[0–31]. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 277 MPC8280. Negated—Indicates that a transaction should not be snooped by MPC8280. (In addition, certain non-global transactions are snooped for reservation coherency.) Timing Comments Assertion/Negation—Same as A[0–31]. MOTOROLA Chapter 7. 60x Signals For More Information On This Product, Go to: www.freescale.com...
  • Page 278 .Following are the state meaning and timing comments for AACK as an output signal. State Meaning Asserted—Indicates that the address tenure of a transaction is terminated. On the cycle following the assertion of AACK, the bus 7-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 279 Negation—Occurs the second bus cycle after the assertion of AACK. Since this signal may be simultaneously driven by multiple devices, it negates in a unique fashion. First the buffer goes to high MOTOROLA Chapter 7. 60x Signals 7-11 For More Information On This Product,...
  • Page 280 Section 8.5.1, “Data Bus Arbitration.” 7.2.6.1 Data Bus Grant (DBG) The data bus grant signal (DBG) is an output/input on the MPC8280. 7-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 281 The data bus busy (DBB) signal is both an input and output signal on the MPC8280. 7.2.6.2.1 Data Bus Busy (DBB)—Output Following are the state meaning and timing comments for the DBB output signal. MOTOROLA Chapter 7. 60x Signals 7-13 For More Information On This Product,...
  • Page 282 7.2.7.1.1 Data Bus (D[0–63])—Output Following are the state meaning and timing comments for the D[0–63] output signals. 7-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 283 Following are the state meaning and timing comments for the DP[0–7] output signals. State Meaning Asserted/Negated—Represents odd parity for each of 8 bytes of data write transactions. Odd parity means that an odd number of bits, MOTOROLA Chapter 7. 60x Signals 7-15 For More Information On This Product,...
  • Page 284 Section 8.5, “Data Tenure Operations.” 7.2.8.1 Transfer Acknowledge (TA) The transfer acknowledge (TA) signal is both input and output on the MPC8280. 7-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 285 If it is the last or only data beat, this also terminates the data tenure. MOTOROLA Chapter 7. 60x Signals 7-17 For More Information On This Product,...
  • Page 286 Negation—TEA must be negated no later than the negation of DBB. 7.2.8.2.2 Transfer Error Acknowledge (TEA)—Output Following are the state meaning and timing comments for the TEA output. 7-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 287 (Note: when the MPC8280 processor is configured for 1:1 clock mode and is performing a burst read into the data cache, the MPC8280 requires MOTOROLA Chapter 7. 60x Signals 7-19 For More Information On This Product,...
  • Page 288 For a burst transfer, PSDVAL may be negated between beats to insert one or more wait states before the completion of the next beat. 7-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 289 Kill An operation that causes a cache block to be invalidated in the cache without writing any modified data to memory. MOTOROLA Chapter 8. The 60x Bus For More Information On This Product, Go to: www.freescale.com...
  • Page 290 In single-MPC8280 bus mode, the MPC8280 is the only bus device in the system. The internal memory controller controls all devices on the external pins. Figure 8-1 shows the signal connections for single-MPC8280 bus mode. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 291 The 60x-compatible bus mode can include one or more potential external masters (for example, an L2 cache, an ASIC DMA, a high-end processor that implements the PowerPC architecture, or a second MPC8280). When operating in a multiprocessor configuration, the MOTOROLA Chapter 8. The 60x Bus For More Information On This Product,...
  • Page 292 Figure 8-3 shows a data transfer that consists of a single-beat MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 293 In burst or port-size accesses, data termination signals indicate the completion of individual beats and, after the final data beat, the end of the tenure. MOTOROLA Chapter 8. The 60x Bus For More Information On This Product,...
  • Page 294 • When no bus device is requesting the address bus, the MPC8280 parks the device selected in the arbiter configuration register on the bus. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 295 When a MPC8280’s internal master needs the 60x bus, it asserts the internal bus request along with the request level. The arbiter asserts the internal bus grant for the highest priority request. MOTOROLA Chapter 8. The 60x Bus For More Information On This Product,...
  • Page 296 In both cases, the pending transaction by the processor is cancelled and BR is negated. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 297 The MPC8280 pipelines data bus operations in strict order with the associated address operations. Figure 8-5 shows how address pipelining allows address tenures to overlap the associated data tenures. MOTOROLA Chapter 8. The 60x Bus For More Information On This Product,...
  • Page 298 Table 8-2 describes the MPC8280’s action as master, slave, and snooper. 8-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 299 Address only Not applicable Not applicable Not applicable Address-only operation. AACK is asserted; MPC8280 takes no further action. 1XX01 Reserved — Not applicable Not applicable Not applicable Illegal customer MOTOROLA Chapter 8. The 60x Bus 8-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 300 • For reads, the processor cleans or flushes during a snoop based on the TBST input. The processor cleans for single-beat reads (TBST negated) to emulate read-with-no-intent-to-cache operations. 8-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 301 The MPC8280 uses four double word burst transactions for transferring cache blocks. For these transactions, TSIZ[0–3] are encoded as 0b0010, and address bits A[27–28] determine which double-word is sent first. MOTOROLA Chapter 8. The 60x Bus 8-13 For More Information On This Product,...
  • Page 302 Double Word Starting Address: Data Transfer A[27–28] = 00 A[27–28] = 01 A[27–28] = 10 A[27–28] = 11 1st data beat 2nd data beat 8-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 303 0 0 1 0 1 0 0 — — — — — — 0 0 1 0 1 1 0 — — — — — — MOTOROLA Chapter 8. The 60x Bus 8-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 304 2nd access 0 1 1 1 0 0 — — — — — Aligned 1 0 0 1 0 0 — — — — 8-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 305 64-bit bus is assumed. Figure 8-6. shows the device connections on the data bus. Table 8-8 lists the bytes required on the data bus for read cycles. MOTOROLA Chapter 8. The 60x Bus 8-17 For More Information On This Product,...
  • Page 306 D[40–47] D[48–55] D[56–63] 64-Bit Port Size 32-Bit Port Size 16-Bit Port Size 8-Bit Port Size Figure 8-6. Interface to Different Port Size Devices 8-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 307 In single-MPC8280 bus mode, these calculations are internal and do not constrain the system. In 60x-compatible bus mode, the external slave or master must determine the new address MOTOROLA Chapter 8. The 60x Bus 8-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 308 The MPC8280 supports an extended transfer mode that improves bus performance. This should not be confused with the extended bus protocol used to support direct-store 8-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 309 — OP0 OP1 OP2 OP3 OP0 OP1 OP0 (0111) — OP1 OP2 OP3 OP4 OP5 OP6 OP7 — OP1 OP2 OP3 — OP1 OP1 MOTOROLA Chapter 8. The 60x Bus 8-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 310 Byte 3-Byte 5-Byte Byte Word Half 3-Byte Word Word Byte Word Double Stop 6-Byte Byte 5-Byte Half Word Word Half Word Double Stop 8-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 311 Figure 8-7. Note that after recognizing an assertion of ARTRY and aborting the current transaction, the MPC8280 may not run the same transaction the next time it is granted the bus. MOTOROLA Chapter 8. The 60x Bus 8-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 312 TA). This guarantees the relationship between TA and ARTRY such that, in case of an address retry, the data may be cancelled in the chip before it can be forwarded 8-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 313 For example, additional wait states are required when the internal processor is in 1:1 clock mode; this case requires at least one wait state to generate the ARTRY response. MOTOROLA Chapter 8. The 60x Bus 8-25 For More Information On This Product, Go to: www.freescale.com...
  • Page 314 DBG is asserted one cycle after TS if the data bus is not busy. The DBG delay should be used to ensure that ARTRY is not asserted after the first or only TA assertion. For the 8-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 315 Data Bus Transfers and Normal Termination The data transfer signals include D[0–63] and DP[0–7]. For memory accesses, the data signals form a 64-bit data path, D[0–63], for read and write operations. MOTOROLA Chapter 8. The 60x Bus 8-27 For More Information On This Product,...
  • Page 316 In a normal burst transfer, the fourth assertion of TA signals the end of a transfer. CLKOUT ADDR + ATTR AACK PSDVAL D[0–63] Figure 8-8. Single-Beat and Burst Data Transfers 8-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 317 CLKOUT ADDR + ATTR AACK PSDVAL D[0–31] Figure 8-9. 28-Bit Extended Transfer to 32-Bit Port Size MOTOROLA Chapter 8. The 60x Bus 8-29 For More Information On This Product, Go to: www.freescale.com...
  • Page 318 DBG before asserting TEA. The data tenure is terminated by a single assertion of TEA regardless of the port size or whether the data tenure is a single-beat or burst transaction. 8-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 319 When other devices detect the GBL input asserted, they must respond by snooping any addresses broadcast. Normally, GBL reflects the M bit value specified for the memory reference in the corresponding translation descriptor. Care must be taken to minimize the MOTOROLA Chapter 8. The 60x Bus 8-31 For More Information On This Product, Go to: www.freescale.com...
  • Page 320 = Cache line fill SH/CRW = Snoop hit, cacheable read/write SH/CIR = Snoop hit, cache-inhibited read Figure 8-12. MEI Cache Coherency Protocol—State Diagram (WIM = 001) 8-32 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 321 For example, writing a word to memory as a word operation on the bus and then reading in the second byte of that word as a byte operation on the bus. MOTOROLA Chapter 8. The 60x Bus 8-33 For More Information On This Product, Go to: www.freescale.com...
  • Page 322 (left most) byte of the double word on D[0–7]. If the processor interfaces with a true little-endian environment, the system may need to perform byte-lane swapping or other operations external to the processor. 8-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 323 • Support for 66 MHz, 3.3 V specification • Uses a buffer pool for the 60x-PCI bus interface • Makes use of the local bus signals to avoid the need for additional pins MOTOROLA Chapter 9. PCI Bridge For More Information On This Product,...
  • Page 324 MPC8280 60x Bus/Local SDMA MPC8280 60x Interface Internal PCI Bridge I/O Sequencer Buffer Pool Embedded Utilities PCI Interface Regs PCI Bus Figure 9-2. PCI Bridge Structure MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 325 SDMA controller to bring data from the PCI bus memory/IO space into the dual-port RAM, or vice versa. The user can choose if the data buffers, buffer descriptors, MOTOROLA Chapter 9. PCI Bridge For More Information On This Product,...
  • Page 326 60x bus. The 60x bus arbitration-level register (PPC_ALRH) should be programmed so that the PCI request level index (0b0011) has a MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 327 5V back planes. For more information regarding the Hot Swap process, refer to the Hot Swap Specification PICMG 2.1, R1.0, August 3, 1998. MOTOROLA Chapter 9. PCI Bridge For More Information On This Product, Go to: www.freescale.com...
  • Page 328 Double word Represents 32 bits or 2 words or 4 bytes Quad word Represents 64 bits or 2 double-words or 4 words or 8 bytes MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 329 (32 bytes) from the starting address, even though all 32 bytes may not actually be sent to the initiator. MOTOROLA Chapter 9. PCI Bridge For More Information On This Product, Go to: www.freescale.com...
  • Page 330 FRAME is asserted indicates the beginning of the address phase. The address and the bus command code are transferred in that cycle. The next cycle ends the address phase and begins the data phase. MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 331 If AD[1-0] is 0bx1 (a reserved encoding) and the PCI_C/BE[3-0] signals indicate a memory transaction, it executes a target disconnect after the first data phase is completed. Note that AD[1-0] are included in parity calculations. MOTOROLA Chapter 9. PCI Bridge For More Information On This Product,...
  • Page 332 9-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 333 TRDY are asserted on the same clock edge. When either is negated a wait cycle is inserted and no data is transferred. To indicate the last data phase IRDY must be asserted when FRAME is negated. MOTOROLA Chapter 9. PCI Bridge 9-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 334 The termination of a PCI transaction is orderly and systematic, regardless of the cause of the termination. All transactions end when FRAME and IRDY are both negated, indicating the idle cycle. 9-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 335 Note that when an initiator is terminated by STOP, it must negate its REQx signal for a minimum of two PCI clocks (of which one clock is needed for the bus to return to the idle MOTOROLA Chapter 9. PCI Bridge...
  • Page 336 PCI bus but aborts internally. The PCI bridge does not target-abort in this case. 9-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 337 The PCI bridge provides data streaming for PCI transactions to and from prefetchable memory. In other words, when the PCI bridge is a target for a PCI initiated transaction, it supplies or accepts multiple cache lines of data without disconnecting. For PCI transactions MOTOROLA Chapter 9. PCI Bridge 9-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 338 PCI bus in the system. Bits 15 through 11 choose a specific device on the bus. Bits 10 through 8 choose a specific function in the requested device. Bits 7 through 2 choose a 9-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 339 Due to design constraints, the software must write a value to the CONFIG_ADDR register prior to each access to the CONFIG_DATA register, even if the address was not changed. MOTOROLA Chapter 9. PCI Bridge 9-17 For More Information On This Product,...
  • Page 340 When the CONFIG_DATA register is written, the PCI bridge generates a special cycle encoding on 9-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 341 (IRDY and TRDY asserted) involving the PCI bridge. When an address or data parity error is detected, the detected-parity-error bit in the configuration space status register is set (see Section 9.11.2.4, “PCI Bus Status Register”). MOTOROLA Chapter 9. PCI Bridge 9-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 342 SERR is asserted when the PCI bridge detects an address parity error while acting as a target. The system error is 9-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 343 Bus Parking When no devices are requesting the bus, the bus is granted, or parked, for a specified device to prevent the AD, PCI_C/BE and PAR signals from floating. The PCI bridge can be MOTOROLA Chapter 9. PCI Bridge 9-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 344 PCI bridge is the next grant, then the PCI bridge’s grant is removed, and the higher-priority device 2 is awarded the next grant. 9-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 345 PCI memory transaction to non-prefetchable space. An address decode flow chart for transactions from the 60x bus masters to the PCI bridge is shown in Figure 9-11. MOTOROLA Chapter 9. PCI Bridge 9-23 For More Information On This Product,...
  • Page 346 2 with ATUs and one with PIMMR. An address decode flow chart for transactions from a PCI bus master to the PCI bridge is shown in Figure 9-12. 9-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 347 PCI-bridge registers without wasting an inbound translation window. In effect, there are a total of three inbound windows, 2 with ATUs and 1 with PIMMR. MOTOROLA Chapter 9. PCI Bridge 9-25 For More Information On This Product,...
  • Page 348 Figure 9-14. Note that the translation mechanism shown is an example only; the address translation, as well as the memory and I/O destinations, can be programmed independently for each address translation window. 9-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 349 MOTOROLA Chapter 9. PCI Bridge 9-27 For More Information On This Product,...
  • Page 350 Software can move the translation base addresses during run-time to access different portions of local memory, but be sure that the PCI inbound translation windows do not overlap. 9-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 351 PCI outbound translation windows do not overlap. Also note that the PCI outbound translation windows should not overlap with the PCI bridge internal register space defined by the PIMMR. MOTOROLA Chapter 9. PCI Bridge 9-29 For More Information On This Product, Go to: www.freescale.com...
  • Page 352 TEA if the 60x bus monitor is activated. The system can recover only after a soft reset. 9-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 353 DMA 0 byte count register (DMABCR0) 0x0000_0000 9.13.1.6.6/-99 0x10524 DMA 0 next descriptor address register (DMANDAR0) 0x0000_0000 9.13.1.6.7/-100 0x10580 DMA 1 mode register (DMAMR1) 0x0000_0000 9.13.1.6.1/-94 MOTOROLA Chapter 9. PCI Bridge 9-31 For More Information On This Product, Go to: www.freescale.com...
  • Page 354 0x1087C General purpose control register (GPCR) 0x0000_0000 9.11.1.7/-37 0x10880 PCI general control register (PCI_GCR) 0x0000_0000 9.11.1.8/-38 0x10884 Error status register (ESR) 0x0000_0000 9.11.1.9/-39 9-32 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 355 PCI address space for locally generated transactions that hit within the outbound translation windows. The new translated address is created by concatenating the transaction offset to this translation address. Refer to Section 9.10.2.2, “PCI Outbound Translation.” MOTOROLA Chapter 9. PCI Bridge 9-33 For More Information On This Product,...
  • Page 356 0x1080A (POBAR0); 0x10822 (POBAR1); 0x1083A (POBAR2) Field Reset 0000_0000_0000_0000 Addr 0x10808 (POBAR0); 0x10820 (POBAR1); 0x10838 (POBAR2) Figure 9-18. PCI Outbound Base Address Registers (POBARx) 9-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 357 0 PCI memory 1 PCI I/O Prefetchable This bit indicates that the address space is prefetchable, so streaming can occur 0 not prefetchable 1 prefetchable MOTOROLA Chapter 9. PCI Bridge 9-35 For More Information On This Product, Go to: www.freescale.com...
  • Page 358 Table 9-7 describes PTCR fields. Table 9-7. PTCR Field Descriptions Bits Name Description Enable Discard timer enable. 0 Disable the discard timer 1 Enable the discard timer 9-36 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 359 Field — DMABC — Reset 0000_0000_0000_0000 Addr 0x1087E Field — INTPCI MCP2PCI — LE_MODE Reset 0000_0000_0000_0000 Addr 0x1087C Figure 9-21. General Purpose Control Register (GPCR) MOTOROLA Chapter 9. PCI Bridge 9-37 For More Information On This Product, Go to: www.freescale.com...
  • Page 360 The PCI general control register (PCI_GCR), shown in Figure 9-22, contains a bit for controlling the PCI reset signal when in host mode. 9-38 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 361 I2O_ I2O_ PERR_ PERR_ PCI_ TAR_ ADDR_ Field — PAR_ PAR_ DBMC IPQO OFQO SERR Reset 0000_0000_0000_0000 Addr 0x10884 Figure 9-23. Error Status Register (ESR) MOTOROLA Chapter 9. PCI Bridge 9-39 For More Information On This Product, Go to: www.freescale.com...
  • Page 362 Each mask bit is active high. That is, if a bit value is zero, an interrupt or machine check is not asserted for the corresponding error condition. 9-40 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 363 PCI write data parity error. The MPC8280 sources PERR. This error is only a function of data. PCI_ADDR_PAR PCI address parity error (read or write). MOTOROLA Chapter 9. PCI Bridge 9-41 For More Information On This Product, Go to: www.freescale.com...
  • Page 364 PCI parity error received on a read PCI_SERR PCI SERR received PCI_TAR_ABT PCI target abort PCI_NO_RSP PCI no response (no DEVSEL; master abort) 9-42 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 365 9.11.1.13 PCI Error Data Capture Register (PCI_EDCR) The PCI error data capture register (PCI_EDCR), shown in Figure 9-27, stores the data associated with the first PCI error captured. MOTOROLA Chapter 9. PCI Bridge 9-43 For More Information On This Product,...
  • Page 366 PCI error captured. Field — — Reset 0000_0000_0000_0000 Addr 0x108A2 Field — — Reset 0000_0000_0000_0000 Addr 0x108A0 Figure 9-28. PCI Error Control Capture Register (PCI_ECCR) 9-44 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 367 PCI bus. The new translated address is created by concatenating the transaction offset to this base address. Refer to Section 9.10.2.1, “PCI Inbound Translation.” MOTOROLA Chapter 9. PCI Bridge 9-45 For More Information On This Product,...
  • Page 368 However, if the PCI bridge is defined as the PCI host, it may be easier to configure its own inbound base address by writing directly to the PIBARx registers. 9-46 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 369 Section 9.11.2.22, “PCI Bus Function Register”) can be cleared to enable the host to configure the device. Some of the fields of this registers are tied to the GPLABARx registers; see Section 9.11.2.14, “General Purpose Local Access Base Address Registers (GPLABARx).” MOTOROLA Chapter 9. PCI Bridge 9-47 For More Information On This Product,...
  • Page 370 This is the smallest window size allowed. PICMR = 0b1xxx_xxxx_xxxx_1111_1111_1111_0000_0000 The mask is 12 bits (physical address bits 31-20) which corresponds to a 1Mbyte window size. 9-48 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 371 Sub system vendor ID 0x0000 9.11.2.15 / 59 Sub system device ID 0x0000 9.11.2.16 / 60 Reserved — — — Capabilities pointer 0x48 9.11.2.17 / 60 MOTOROLA Chapter 9. PCI Bridge 9-49 For More Information On This Product, Go to: www.freescale.com...
  • Page 372 66. The registers are accessible from the PCI bus through the PCI configuration transaction when the PCI bridge is in agent mode. 9-50 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 373 Figure 9-33. Vendor ID Register Table 9-20. Vendor ID Register Description Bits Name Description 15–0 Vendor ID Identifies the manufacturer of the device (0x1057 = Motorola) 9.11.2.2 Device ID Register Figure 9-34 and Table 9-21 describes the device ID register. Field Reset 0001_1000_1100_0000...
  • Page 374 The PCI bus status register, shown in Figure 9-36, is used to record status information for PCI bus-related events. Only 2-byte accesses to address offset 0x06 are allowed. 9-52 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 375 PCI bus. Capabilities List Hardwired to 1, indicating that the PCI bridge implements new capabilities on the PCI bus. 3–0 — Reserved, should be cleared. MOTOROLA Chapter 9. PCI Bridge 9-53 For More Information On This Product, Go to: www.freescale.com...
  • Page 376 Revision Specifies a device-specific revision code for the MPC8280 (assigned Dependent by Motorola). Revision ID = 0x11 for .25 micron revisions A.0, B.1, and 9.11.2.6 PCI Bus Programming Interface Register Figure 9-38 and Table 9-25 describe the PCI bus programming interface register.
  • Page 377 0x01, 0x00, and 0x0E respectively, indicating that the MPC8280 supports the I O protocol. The user should note that the I O support is not fully standard compliant. MOTOROLA Chapter 9. PCI Bridge 9-55 For More Information On This Product, Go to: www.freescale.com...
  • Page 378 2–0 Read-only least-significant bits of the latency timer. (The latency timer value is programmed in multiples of eight.) 9-56 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 379 MPC8280’s internal memory-mapped registers. Transactions from PCI that “hit” the PIMMRBAR are translated to the IMMR and sent to the logic that controls the internal memory-mapped registers. PIMMRBAR is shown in Figure 9-45. MOTOROLA Chapter 9. PCI Bridge 9-57 For More Information On This Product, Go to: www.freescale.com...
  • Page 380 Similarly, a write to PIBARx causes a write to GPLABARx of the non-masked bits of the base address. GPLABARx is shown in Figure 9-46. 9-58 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 381 9.11.2.15 Subsystem Vendor ID Register Figure 9-47 and Table 9-34 describe the subsystem vendor ID register. Field SVID Reset 0000_0000_0000_0000 Addr 0x2C Figure 9-47. Subsystem Vendor ID Register MOTOROLA Chapter 9. PCI Bridge 9-59 For More Information On This Product, Go to: www.freescale.com...
  • Page 382 Table 9-36. PCI Bus Capabilities Pointer Register Description Bits Name Description 7–0 Capabilities pointer Specifies the byte offset in the configuration space containing the first item in the capabilities list. 9-60 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 383 Table 9-38. PCI Bus Interrupt Pin Register Description Bits Name Description 7–0 Interrupt Pin Indicates which interrupt pin the device (or function) uses (0x01 = INTA). MOTOROLA Chapter 9. PCI Bridge 9-61 For More Information On This Product, Go to: www.freescale.com...
  • Page 384 Specifies how often the device needs to gain access to the PCI bus. The value 0x00 indicates that the PCI bridge has no major requirements for the settings of latency timers. 9-62 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 385 PCI_HA Set or cleared by a Power-On configuration bit on power-up and is read-only. 0 PCI interface is in host mode 1 PCI interface is in agent mode MOTOROLA Chapter 9. PCI Bridge 9-63 For More Information On This Product,...
  • Page 386 Determines the PCI bridge’s arbitration priority. Priority 0 The PCI bridge has a low priority. 1 The PCI bridge has a high priority. 9-64 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 387 Figure 9-57 and Table 9-44 describe the Hot Swap control status register. Field — — — Reset 0000_0000 Addr 0x4A Figure 9-57. Hot Swap Control Status Register MOTOROLA Chapter 9. PCI Bridge 9-65 For More Information On This Product, Go to: www.freescale.com...
  • Page 388 That is, the data appears in the core register in ascending significance byte order (LSB to MSB). 9-66 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 389 PCI bus, share memory with the MPC8280, it is recommended to leave the MPC8280's 603e core CPU and peripheral logic in the big endian (BE) modes and then to use a region of the MPC8280 local memory for LE-formatted data. When a little endian PCI device MOTOROLA Chapter 9. PCI Bridge 9-67 For More Information On This Product, Go to: www.freescale.com...
  • Page 390 5. Therefore, the munged address of this register would be 0x04710504. Therefore, to set CTM in PCI DMA0 mode register, 0x00000004 is written to 0x04710504. 9-68 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 391 Note that the data structure description assumes the following: • Addresses refer to 60x bus addresses. • Address and data byte ordering are big-endian. MOTOROLA Chapter 9. PCI Bridge 9-69 For More Information On This Product,...
  • Page 392 The PCI bridge’s message unit can operate with either generic messages and door bell registers, or as an I O interface. 9-70 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 393 Outbound Message Registers (OMRx) The outbound message registers, described in Figure 9-61 and Figure 9-47, are accessible from the PCI bus and the 60x bus in both host and agent modes. MOTOROLA Chapter 9. PCI Bridge 9-71 For More Information On This Product,...
  • Page 394 ODR, described in Figure 9-62 and Table 9-48, is accessible from the PCI bus and the 60x bus in both host and agent modes. 9-72 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 395 Field IMC IDRx Reset 0000_0000_0000_0000 Addr 0x1046A Field IDRx Reset 0000_0000_0000_0000 Addr 0x10468 Figure 9-63. Inbound Doorbell Register (IDR) MOTOROLA Chapter 9. PCI Bridge 9-73 For More Information On This Product, Go to: www.freescale.com...
  • Page 396 FIFO). The other FIFO keeps track of the MFAs which have posted messages (Post_LIST FIFO). Figure 9-64 shows an example of the message queues, although there is no specific order that these queues must follow. 9-74 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 397 PCI configuration space to the host. Refer to the following: • Section 9.11.2.6, “PCI Bus Programming Interface Register” • Section 9.11.2.7, “Subclass Code Register” • Section 9.11.2.8, “PCI Bus Base Class Code Register” MOTOROLA Chapter 9. PCI Bridge 9-75 For More Information On This Product, Go to: www.freescale.com...
  • Page 398 Inbound free_fifo head pointer. Local memory offset of the head pointer of the inbound free list FIFO. 1–0 — Reserved, should be cleared. 9-76 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 399 IPTPR. After the local processor has read the message pointed to by the MFA, the local processor must advance the IPTPR. Once the processor has completed use of the message, it must return the message buffer (i.e. MFA) to the inbound free list FIFO. MOTOROLA Chapter 9. PCI Bridge 9-77 For More Information On This Product, Go to: www.freescale.com...
  • Page 400 MFAs posted by PCI hosts are picked up by the local processor via the inbound post_FIFO tail pointer register, described in Figure 9-68 and Table 9-53. The local processor is responsible for updating this register. 9-78 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 401 Section 9.12.3.4.2, “Outbound FIFO Queue Port Register (OFQPR)”). The PCI bridge’s O unit then writes the MFA to the OFHPR. This, in turn, causes the outbound free head pointer to be advanced. MOTOROLA Chapter 9. PCI Bridge 9-79 For More Information On This Product,...
  • Page 402 Free MFAs are picked up by the local processor pointed to by the outbound free_FIFO tail pointer register, described in Figure 9-70 and Table 9-55. This register is updated by the local processor. 9-80 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 403 The local processor posts MFAs to the outbound post list FIFO that is pointed to by the outbound post_FIFO head pointer register, described in Figure 9-71 and Table 9-56. The local processor is responsible for updating this register. MOTOROLA Chapter 9. PCI Bridge 9-81 For More Information On This Product, Go to: www.freescale.com...
  • Page 404 Hardware automatically advances this register after every read. Field OPTP Reset 0000_0000_0000_0000 Addr 0x104DA Field OPTP — Reset 0000_0000_0000_0000 Addr 0x104D8 Figure 9-72. Outbound Post_FIFO Tail Pointer Register (OPTPR) 9-82 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 405 OFQPR is used by PCI masters to access outbound messages in local memory. Local processor does not have access to this port. OFQPR should be accessed only from the PCI bus. OFQPR is described in Figure 9-74 and Table 9-59. MOTOROLA Chapter 9. PCI Bridge 9-83 For More Information On This Product, Go to: www.freescale.com...
  • Page 406 Field — OPQI — — OM1I OM0I Reset 0000_0000_0000_0000 Refer to Table 9-60. Addr 0x10430 Figure 9-75. Outbound Message Interrupt Status Register (OMISR) 9-84 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 407 0x10436 Field — OPQIM — ODIM — OM1IM OM0IM Reset 0000_0000_0000_0000 Refer to Table 9-61. Addr 0x10434 Figure 9-76. Outbound Message Interrupt Mask Register (OMIMR) MOTOROLA Chapter 9. PCI Bridge 9-85 For More Information On This Product, Go to: www.freescale.com...
  • Page 408 OFOI IPOI — IPQI — IM1I IM0I Reset 0000_0000_0000_0000 Refer to Table 9-62. Addr 0x10480 Figure 9-77. Inbound Message Interrupt Status Register (IMISR) 9-86 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 409 Addr 0x10486 Field — OFOIM IPOIM — IPQIM MCIM IDIM — IM1IM IM0IM Reset 0000_0000_0000_0000 Addr 0x10484 Figure 9-78. Inbound Message Interrupt Mask Register (IMIMR) MOTOROLA Chapter 9. PCI Bridge 9-87 For More Information On This Product, Go to: www.freescale.com...
  • Page 410 FIFOs. MUCR should be accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from the PCI bus have undefined results. 9-88 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 411: Reset 0000_0000_0000_0000

    This register specifies the beginning of the circular queue structure in local memory. The following QBAR should be accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from the PCI bus have undefined results. MOTOROLA Chapter 9. PCI Bridge 9-89 For More Information On This Product, Go to: www.freescale.com...

  • Page 412: Reset 0000_0000_0000_0000

    • Interrupt on completed segment, chain, and error • Supports all transfer combinations between 60x memory and PCI memory: 60x-to-60x, PCI-to-PCI, 60x-to-PCI, and PCI-to-60x. 9-90 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 413 The DMA controller attempts to read a full cache line whenever possible. Writing to PCI memory depends on the alignment of the destination address and the size of the transfer. MOTOROLA Chapter 9. PCI Bridge 9-91 For More Information On This Product, Go to: www.freescale.com...
  • Page 414 Other control parameters in the mode register can also be initialized here if necessary. • First clear then set the CS (channel start) bit in the mode register to start the DMA transfer. 9-92 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 415 DMA controller begins writing data from the queue to PCI memory space beginning at the destination address. The process is repeated until there is no more data to transfer or an error condition has occurred on the PCI bus. MOTOROLA Chapter 9. PCI Bridge 9-93 For More Information On This Product, Go to: www.freescale.com...
  • Page 416 Reset 0000_0000_0000_0000 Addr 0x10500 (DMAMR0); 0x10580 (DMAMR1); 0x10600 (DMAMR2); 0x10680 (DMAMR3) Figure 9-82. DMA Mode Registers 0–3 (DMAMRx) Table 9-66 describes DMAMRx fields. 9-94 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 417 MOTOROLA Chapter 9. PCI Bridge 9-95 For More Information On This Product,...
  • Page 418 0x10506(DMASR0); 0x10586 (DMASR1); 0x10606 (DMASR2); 0x10686 (DMASR3) Field — — EOSI EOCDI Reset 0000_0000_0000_0000 Addr 0x10504 (DMASR0); 0x10584(DMASR1); 0x10604 (DMASR2); 0x10684 (DMASR3) Figure 9-83. DMA Status Registers 0–3 (DMASRx) 9-96 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 419 0x1050A(DMACDR0); 0x1058A (DMACDR1); 0x1060A (DMACDR2); 0x1068A (DMACDR3) Field SNEN EOSIE — Reset 0000_0000_0000_0000 Addr 0x10508 (DMACDR0); 0x10588 (DMACDR1); 0x10608 (DMACDR2); 0x10688 (DMACDR3) Figure 9-84. DMA Current Descriptor Address Registers 0–3 (DMACDARx) MOTOROLA Chapter 9. PCI Bridge 9-97 For More Information On This Product, Go to: www.freescale.com...

  • Page 420: Reset 0000_0000_0000_0000

    Table 9-69 describes DMASARx fields. Table 9-69. DMASARx Field Descriptions Name Description 31–0 Source address of DMA transfer. The content is updated after every DMA read operation. 9-98 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 421 Destination address. The content is updated after every DMA write operation. 9.13.1.6.6 DMA Byte Count Registers 0–3 (DMABCRx) This register contains the number of bytes per transfer (maximum transfer size is 64 Mbytes). MOTOROLA Chapter 9. PCI Bridge 9-99 For More Information On This Product, Go to: www.freescale.com...
  • Page 422 NDSNE NDEOSIE — Reset 0000_0000_0000_0000 Addr 0x10524 (DMANDAR0); 0x105A4 (DMANDAR1); 0x10624 (DMANDAR2); 0x106A4 (DMANDAR3) Figure 9-88. DMA Next Descriptor Address Registers 0–3 (DMANDARx) 9-100 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 423 DMA transfer with the control parameters specified by the descriptor. The DMA controller traverses the descriptor chain until reaching the last descriptor (with its EOTD bit set). MOTOROLA Chapter 9. PCI Bridge 9-101 For More Information On This Product,...
  • Page 424 /* 0x1122334455667788 double word double b; /* 0x55667788aabbccdd double word double c; /* 0x8765432101234567 double word */ double d; /* 0x0123456789abcdef double word */ 9-102 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 425 Refer to section 9.11.1.9 through section 9.11.1.14. The PCI bridge detects illegal transfer sizes to its configuration registers, PCI master-abort cycles, PCI received target-abort errors, PCI parity errors, and overflow/underflow errors MOTOROLA Chapter 9. PCI Bridge 9-103 For More Information On This Product,...
  • Page 426 When an error is detected, the associated information is latched inside these registers until all the associated error flags are cleared. 9-104 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 427 The PCI bridge sets bit 2 of the error status register. If the PCI command register of the PCI bridge is programmed to respond to parity errors (bit 6 of the PCI command register is set) the PCI bridge reports the error to the PCI target by asserting MOTOROLA Chapter 9. PCI Bridge 9-105 For More Information On This Product, Go to: www.freescale.com...
  • Page 428 (ESR)”). It indicates that an error has occurred on the 60x bus in a transaction that was originally initiated by the PCI bridge. 9-106 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 429 If an external PCI master writes the inbound doorbell register such that the most significant bit is set, then bit 12 of ESR (refer to Section 9.11.1.9, “Error Status Register (ESR)”) is set and a machine check is asserted to the local processor. MOTOROLA Chapter 9. PCI Bridge 9-107 For More Information On This Product, Go to: www.freescale.com...
  • Page 430 Freescale Semiconductor, Inc. Error Handling 9-108 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 431 • A lower clock input frequency reduces overall electromagnetic interference generated by the system • Oscillating at different frequencies eliminates the need for another oscillator MOTOROLA Chapter 10. Clocks and Power Control 10-1 For More Information On This Product,...
  • Page 432 • SCC clocks (SCC_CLK) • Baud-rate generator clock (BRG_CLK) • PCI clock (PCI_CLK) • DLL clocks The PLL synchronizes these clock signals to each other. 10-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 433 SCMR is a read-only register. Its value is determined during power-on reset (PORESET). Refer to Section 10.5, “System Clock Mode Register (SCMR)." Figure 10-1. MPC8280 System Clock Architecture MOTOROLA Chapter 10. Clocks and Power Control 10-3 For More Information On This Product,...
  • Page 434 NOTE All PCI timings are measured relative to CLKIN2, and all 60x bus timings are measured relative to CLKIN1. 10-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 435 VCCSYN, followed by the 10-µF capacitor, and finally the 10-Ω resistor to Vdd. These traces should be kept short and direct. VCCSYN 10ohm 0.1uF 10uF Figure 10-4. PLL Filtering Circuit MOTOROLA Chapter 10. Clocks and Power Control 10-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 436 01 Decimal value of 1; MAIN_CLK divided by 16 (normal operation). 10 Decimal value of 2; MAIN_CLK divided by 64. 11 Decimal value of 3; MAIN_CLK divided by 256. 10-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 437 MODCK[1-3] and MODCK_H. Refer to Section 10.1.4, “Dividers.” (CPM_CLK/CLKIN) is defined as the CPM Multiplication Factor in the MPC8280 Family Hardware Specifications. (CPM_CLK/PCI_CLK) is defined as the CPM Multiplication Factor in the MPC8280 Family Hardware Specifications. MOTOROLA Chapter 10. Clocks and Power Control 10-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 438 For further information and complete lists of each clock mode’s possible clock configurations, see Section 1.3, “Clock Configuration Modes,” in the MPC8280 PowerQUICC II Family Hardware Specifications (order number: MPC8280EC). 10-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 439 The MPC8280 supports the following new features as compared to the MPC860 and MPC850. • The synchronous DRAM machine enables back-to-back memory read or write operations using page mode, pipelined operation and bank interleaving for high-performance systems. MOTOROLA Chapter 11. Memory Controller 11-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 440 60x bus and the local bus. • Flexible UPM assignment—The user can assign any of the three UPMs to the 60x bus or the Local bus 11-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 441 — 32-bit address decoding with mask — Variable block sizes (32 Kbytes to 4 Gbytes) — Three types of data errors check/correction: – Normal odd/even parity MOTOROLA Chapter 11. Memory Controller 11-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 442 — UPM refresh timer runs a user-specified control signal pattern to support refresh — User-specified control-signal patterns can be initiated by software 11-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 443 When a memory address matches BRx[BA], the corresponding machine takes ownership of the external signals that control access and maintains control until the cycle ends. MOTOROLA Chapter 11. Memory Controller 11-5 For More Information On This Product,...
  • Page 444 GPCM. CS1 is used as the RAS signal for 64-bit DRAM with BR1[MS] configured to select UPMA. BS[0–7] are used as CAS signals on the DRAM. 11-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 445 The UPM specifies a set of signal patterns for a user-specified number of clock cycles. The UPM RAM pattern run by the memory controller is selected according to the type of external access transacted. At every clock cycle, MOTOROLA Chapter 11. Memory Controller 11-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 446 60x bus are ignored. 60x-to-local bus transactions have priority over regular memory bank hits. 11-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 447 SIUMCR[EPAR] programming. 11.2.5 Transfer Error Acknowledge (TEA) Generation The memory controller asserts the transfer error acknowledge signal (TEA) in the following cases: MOTOROLA Chapter 11. Memory Controller 11-9 For More Information On This Product, Go to: www.freescale.com...
  • Page 448 • Write-after-read (WARA). When a read access hits a memory bank in which ATOM = 10, the MPC8280 locks the bus for the exclusive use of the accessing master (internal or external). 11-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 449 This feature allows multiple MPC8280 systems to be connected in 60x-compatible mode without losing functionality and performance. It also makes it easy to connect other 60x-compatible slaves on the 60x bus. MOTOROLA Chapter 11. Memory Controller 11-11 For More Information On This Product,...
  • Page 450 Table 11-1. Number of PSDVAL Assertions Needed for TA Assertion Port Size Transfer Size PSDVAL Assertions TA Assertions Double word Word/half word/byte (32-bit aligned) Double Word Word 11-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 451 Size Device Size Device Device BADDR[27] N.C. Connected N.C. Connected Connected Connected BADDR[28] N.C. Connected N.C. Connected Connected Connected BADDR[29] N.C. N.C. Connected Connected Connected MOTOROLA Chapter 11. Memory Controller 11-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 452 Each register also includes a memory attribute and selects the machine for memory operation handling. Figure 11-7 shows the BRx register format. 11-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 453 1 Only read accesses are allowed. The memory controller does not assert CSx and PSDVAL on write cycles to this memory bank. TESCR1[WP] or L_TESCR1[WP] (depending on which bus is being used) is set if a write to this memory bank is attempted. MOTOROLA Chapter 11. Memory Controller 11-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 454 The ORx registers define the sizes of memory banks and access attributes. The ORx attributes bits support the following three modes of operation as defined by BR[MS]. • SDRAM mode 11-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 455 Note: If xSDMR[PBI] = 0, the maximum size of the memory bank should not exceed 128 Mbytes. 12–16 LSDAM Lower SDRAM address mask. Clearing LSDAM implements a minimum size of 1 Mbyte. MOTOROLA Chapter 11. Memory Controller 11-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 456 IBID should be set in 60x-compatible mode if the SDRAM device is not connected to the BANKSEL pins. 28–31 — Reserved, should be cleared. Figure 11-8 shows ORx as it is formatted for GPCM mode. 11-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 457 10 CS is output a quarter of a clock after the address lines 11 CS is output half a clock after the address lines (default) Note: After a system reset, OR0[ACS] = 11. MOTOROLA Chapter 11. Memory Controller 11-19 For More Information On This Product,...
  • Page 458 Therefore, when the other conditions occur, it is necessary that SCY ≠ 0000. Figure 11-9 shows ORx as it is formatted for UPM mode. 11-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 459 01 One idle clock cycle is inserted. 10 Four idle clock cycles are inserted. 11 Eight idle clock cycles are inserted. — Reserved, should be cleared. MOTOROLA Chapter 11. Memory Controller 11-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 460 Address multiplex size. Determines how the address of the current memory cycle can be output on the address pins. See Section 11.4.5.2, “SDRAM Address Multiplexing (SDAM and BSMA).” 11-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 461 See Section 11.4.6.2, “Activate to Read/Write Interval.” ACTIVATE 001 1 clock cycle 010 2 clock cycles 111 7 clock cycles 000 8 clock cycles MOTOROLA Chapter 11. Memory Controller 11-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 462 CAS latency. Defines the timing for first read data after SDRAM samples a column address. See Section 11.4.6.3, “Column Address to First Data Out—CAS Latency.” 00 Reserved 01 1 10 2 11 3 11-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 463 001 A9 010 A10 010 A8 011 A9 011 A7 100 A8 100 A6 101 A7 101 A5 110 A6 110 A4 111 A5 111 A3 MOTOROLA Chapter 11. Memory Controller 11-25 For More Information On This Product, Go to: www.freescale.com...
  • Page 464 SDRAM. See Section 11.4.6.5, “Last Data In to Precharge—Write Recovery.” 01 1 clock cycles 10 2 clock cycles 11 3 clock cycles 00 4 clock cycles 11-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 465 0x10170 (MAMR); 0x10174 (MBMR); 0x10178 (MCMR) Field RLFx WLFx TLFx Reset 0000_0000_0000_0000 Addr 0x10172 (MAMR); 0x10176 (MBMR); 0x1017A (MCMR) Figure 11-11. Machine x Mode Registers (MxMR) MOTOROLA Chapter 11. Memory Controller 11-27 For More Information On This Product, Go to: www.freescale.com...
  • Page 466 Note: To avoid conflicts between successive accesses to different memory regions, the minimum pattern in the RAM array for a request serviced should not be shorter than the period established by DSx. 11-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 467 The memory data register (MDR), shown in Figure 11-12, contains data written to or read from the RAM array for UPM commands. MDR must be set up before READ WRITE issuing a write command to the UPM. MOTOROLA Chapter 11. Memory Controller 11-29 For More Information On This Product, Go to: www.freescale.com...
  • Page 468 The memory address register (MAR) is shown in Figure 11-13. Field Reset xxxx_xxxx_xxxx_xxxx Addr 0x10168 Field Reset xxxx_xxxx_xxxx_xxxx Addr 0x10116A Undefined at reset. Figure 11-13. Memory Address Register (MAR) 11-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 469 The local bus assigned UPM refresh timer register (LURT) is shown in Figure 11-15. Field LURT Reset 0000_0000 Addr 0x101A0 Figure 11-15. Local Bus-Assigned UPM Refresh Timer (LURT) MOTOROLA Chapter 11. Memory Controller 11-31 For More Information On This Product, Go to: www.freescale.com...
  • Page 470 MPTPR[PTP] = 31, the PSRT value should be 11decimal. (12*32)/25 MHz = 15.36 µs, which is less than the required service period of 15.6 µs. 11-32 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 471 11.3.12 Memory Refresh Timer Prescaler Register (MPTPR) Figure 11-18 shows the memory refresh timer prescaler register (MPTPR). Field — Reset undefined Addr 0x10184 Figure 11-18. Memory Refresh Timer Prescaler Register (MPTPR) MOTOROLA Chapter 11. Memory Controller 11-33 For More Information On This Product, Go to: www.freescale.com...
  • Page 472 Table 11-18. SDRAM Interface Signals 60x Bus Local Bus Comments CS[0–11] Device select PSDRAS LSDRAS SDCAS LSDCAS SDWE LSDWE SDA10 LSDA10 “A10” control DQM[0–7] LDQM[0–3] Byte select 11-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 473 Figure 11-19. shows an eight-bank, 128-Mbyte system. Each bank consists of eight 2 x 1-Mbit x 8 SDRAMs. Note that the SDRAM memory clock must operate at the same frequency as, and be phase-aligned with, the system clock. MOTOROLA Chapter 11. Memory Controller 11-35 For More Information On This Product, Go to: www.freescale.com...
  • Page 474 2x1M x8 2x1M x8 SDRAM SDRAM ADDR[0–11] ADDR[0–11] DQ[0–7] DQ[0–7] DATA[0–7] DATA[56–63] Figure 11-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown) 11-36 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 475 The SDRAM device samples the command and data inputs on the rising edge of the MPC8280 bus clock. Data at the output of the SDRAM device must be sampled on the rising edge of the MPC8280 bus clock. MOTOROLA Chapter 11. Memory Controller 11-37 For More Information On This Product, Go to: www.freescale.com...
  • Page 476 CPM accesses and with one clock of separation for core accesses, as required by the 60x bus specification. 11-38 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 477 • If BCR[EAV] is programmed, BNKSEL signals facilitate logic analysis of the system. Otherwise, the logic analyzer equipment must understand the address multiplexing scheme of the board and intelligently reconstruct the address of bus transactions. MOTOROLA Chapter 11. Memory Controller 11-39 For More Information On This Product,...
  • Page 478 The values are stored in the ORx and P/LSDMR registers. These parameters include the following: 11-40 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 479 P/LSDMR register. 11.4.6.1 Precharge-to-Activate Interval As demonstrated in Figure 11-20, this parameter, controlled by P/LSDMR[PRETOACT] defines the earliest timing for activate or refresh command after a precharge command. MOTOROLA Chapter 11. Memory Controller 11-41 For More Information On This Product,...
  • Page 480 READ WRITE ACTIVATE SDRAS SDCAS MA[0–11] DATA ACTTORW = 2 ACTIVATE WRITE Command Command Figure 11-21. ACTTORW = 2 (2 Clock Cycles) 11-42 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 481 SDRAM. It is always related to the CL parameter. Activate Read Deactivate Last Data Out LDOTOPRE = 2 SDRAS SDCAS Column MA[0–11] Data Figure 11-23. LDOTOPRE = 2 (–2 Clock Cycles) MOTOROLA Chapter 11. Memory Controller 11-43 For More Information On This Product, Go to: www.freescale.com...
  • Page 482 PRETOACT = 3 RFRC = 4 (6 clocks) Precharge Activate command Auto refresh Bank A if needed Figure 11-25. RFRC = 4 (6 Clock Cycles) 11-44 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 483 SDRAM command. Figure 11-27 illustrates the timing when BUFCMD equals 1. SDAMUX CMD strobes Activate Read (without cs) MA[0–11] Column Command setup cycle Command setup cycle Figure 11-27. BUFCMD = 1 MOTOROLA Chapter 11. Memory Controller 11-45 For More Information On This Product, Go to: www.freescale.com...
  • Page 484 Figure 11-28. SDRAM Single-Beat Read, Page Closed, CL = 3 SDRAS SDCAS Column MA[0–11] Data Figure 11-29. SDRAM Single-Beat Read, Page Hit, CL = 3 11-46 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 485 * BS—Bank select according to SDRAM organization. A10 = 1 means all banks are precharged. CAS Latency = 3 Figure 11-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3 MOTOROLA Chapter 11. Memory Controller 11-47 For More Information On This Product,...
  • Page 486 SDRAS SDCAS Column1 Column2 MA[0–11] Data DQM latency (affects negation only) = 2 Figure 11-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3 11-48 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 487 DQMn high on the irrelevant cycles of the burst. However, system performance is not compromised since, if a new transaction is pending, the MPC8280 begins executing it immediately, effectively terminating the burst early. MOTOROLA Chapter 11. Memory Controller 11-49 For More Information On This Product, Go to: www.freescale.com...
  • Page 488 The period of the refresh interval must be greater than the access time to ensure that read and write operations complete successfully. 11-50 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 489 SDRAM machine’s mode register (RFRC in P/LSDMR). The timing is shown in Figure 11-39. Activate RFRC SDRAS SDCAS MA[0–11] Data Figure 11-39. SDRAM Bank-Staggered CBR Refresh Timing MOTOROLA Chapter 11. Memory Controller 11-51 For More Information On This Product, Go to: www.freescale.com...
  • Page 490 BNKSEL pins could be incorrect even if the device is connected to the BNKSEL pins. To ensure proper connection, note that BNKSEL0 is msb and BNKSEL2 is lsb as stated in Table 6-1. 11-52 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 491 Consider the following SDRAM organization: • Eight 64 Mbit devices, each organized as 8M x 8bits • Each device has four internal banks, 12 rows, and 9 columns MOTOROLA Chapter 11. Memory Controller 11-53 For More Information On This Product,...
  • Page 492 Table 11-29. Register Settings (Bank-Based Interleaving) Register Settings BA Base address EMEMC0 PS00 = 64-bit port size ATOM00 DECC00 MS010 = SDRAM-60x bus 11-54 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 493 R/W in the timing diagrams. See Section 11.2.7, “Data Buffer Controls (BCTLx and LWR).” Additional control is available in 60x-compatible mode (60x bus only)—ALE–external address latch enable MOTOROLA Chapter 11. Memory Controller 11-55 For More Information On This Product,...
  • Page 494 Write 1/4*Clock -1/4*Clock -1/4*Clock 2+SCY Write 1/2*Clock -1/4*Clock -1/4*Clock 2+SCY Read 2+2*SCY Read (1+1/4)*Clock 3+2*SCY Read (1+1/2)*Clock 3+2*SCY Write 2+2*SCY Write (1+1/4)*Clock 3+2*SCY 11-56 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 495 BCTL0 is connected to the respective R/W in the peripheral device. MPC8280 Peripheral Address Address BCTL0 Data Data Figure 11-41. GPCM Peripheral Device Interface MOTOROLA Chapter 11. Memory Controller 11-57 For More Information On This Product, Go to: www.freescale.com...
  • Page 496 For example, when ACS = 00 and CSNT = 1, WE is negated one quarter of a clock earlier, as shown in Figure 11-44. 11-58 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 497 ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. When TRLX = 1 and ACS ≠ 00, an additional cycle between the address and strobes is inserted by the MPC8280 memory controller. See Figure 11-46 and Figure 11-47. MOTOROLA Chapter 11. Memory Controller 11-59 For More Information On This Product, Go to: www.freescale.com...
  • Page 498 PSDVAL to complete the transfer with zero wait states. The minimum access duration in this case is 3 clock cycles. 11-60 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 499 The timing of the OE is affected only by TRLX. It always asserts and negates on the rising edge of the external bus clock. OE always asserts on the rising clock edge after CS is asserted, and therefore its assertion can be delayed (along with the assertion of CS) by MOTOROLA Chapter 11. Memory Controller 11-61 For More Information On This Product, Go to: www.freescale.com...
  • Page 500 Table 11-32. TRLX and EHTR Combinations Number of Hold Time ORx[TRLX] ORx[EHTR] Clock Cycles See Figure 11-50 through Figure 11-53 for timing examples. 11-62 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 501 Figure 11-50. GPCM Read Followed by Read (ORx[29–30] = 00, Fastest Timing) Clock Address PSDVAL BCTLx Data Hold Time 1-cycle hold time allowed Figure 11-51. GPCM Read Followed by Read (ORx[29–30] = 01) MOTOROLA Chapter 11. Memory Controller 11-63 For More Information On This Product, Go to: www.freescale.com...
  • Page 502 Figure 11-52. GPCM Read Followed by Write (ORx[29–30] = 01) Clock Address PSDVAL BCTLx Data Hold Time Figure 11-53. GPCM Read Followed by Write (ORx[29–30] = 10) 11-64 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 503 Section 5.4, “Reset Configuration.” The boot chip-select does not provide write protection. CS0 operates this way until the first write to OR0 and it can be used as any other chip-select register once the preferred address range is MOTOROLA Chapter 11. Memory Controller 11-65 For More Information On This Product, Go to: www.freescale.com...
  • Page 504 60x and local bus. Table 11-34. UPM Interfaces Signals 60x Bus Local Bus Comments CS[0–11] Device select PBS[0–7] LBS[0–3] Byte Select 11-66 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 505 UPM • A UPM refresh timer expires and requests a transaction, such as a DRAM refresh • A transfer error or reset generates an exception request MOTOROLA Chapter 11. Memory Controller 11-67 For More Information On This Product, Go to: www.freescale.com...
  • Page 506 • Read burst cycle pattern (RBS) • Write single-beat pattern (WSS) • Write burst cycle pattern (WBS) These patterns are described in Section 11.6.1.1, “Memory Access Requests.” 11-68 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 507 BRx. The value in BRx[MS] selects the UPM to handle the memory access. The user must ensure that the UPM is appropriately initialized before a request. MOTOROLA Chapter 11. Memory Controller 11-69 For More Information On This Product, Go to: www.freescale.com...
  • Page 508 UPMC can be assigned to any bus; there is no need to program its refresh routine because it will use the one in UPMA or UPMB, according to the bus to which it is assigned. 11-70 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 509 UPMs in the memory controller for integer and non-integer clock ratios. The clock phases shown reflect timing windows during which generated signals can change state. If specified in the RAM, the value of the external signals can be changed after any of the MOTOROLA Chapter 11. Memory Controller 11-71 For More Information On This Product, Go to: www.freescale.com...
  • Page 510 T1, T2, T3, or T4 (there is a propagation delay specified in the Hardware Specifications). Note however that only the CS signal corresponding to the currently 11-72 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 511 Figure 11-61. The signals at the bottom of Figure 11-61. are UPM outputs. The selected CS is for the bank that matches the current address. The selected BS is for the byte lanes read or written by the access. MOTOROLA Chapter 11. Memory Controller 11-73 For More Information On This Product, Go to: www.freescale.com...
  • Page 512 — Addr (All 32 bits of the RAM word are addressed as shown in the address row above.) Figure 11-62. The RAM Word 11-74 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 513 10 The value of the GPL0 line at the rising edge of T3 will be 0 11 The value of the GPL0 line at the rising edge of T3 will be 1 See Section 11.6.4.1.3, “General-Purpose Signals (GxTx, GOx).” MOTOROLA Chapter 11. Memory Controller 11-75 For More Information On This Product, Go to: www.freescale.com...
  • Page 514 1 A freeze in the external signal’s logical value occurs if the external wait signal is detected asserted. This condition lasts until UPMWAITx is negated. 11-76 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 515 10 A[0–31] is the address requested by the internal master multiplexed according to MxMR[AMx]. For example, row address. 11 A[0–31] is the contents of MAR. Used for example, during SDRAM mode initialization. MOTOROLA Chapter 11. Memory Controller 11-77 For More Information On This Product,...
  • Page 516 The selected UPM affects only assertion and negation of the appropriate CS signal. The state of the selected CSx signal of the corresponding bank depends on the value of each CSTn bit. 11-78 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 517 The uppermost byte select (BS0) indicates that D[0–7] contains valid data during a cycle. Likewise, BS1 indicates that D[8–15] contains valid data, BS2 indicates that D[16–23] contains valid data, and BS3 indicates that D[24–31] contains valid data during a cycle, and MOTOROLA Chapter 11. Memory Controller 11-79 For More Information On This Product, Go to: www.freescale.com...
  • Page 518 RAM words. Setting the REDO bits of the RAM word to a nonzero value to cause the UPM to reexecute the current RAM word up to three times, according to Table 11-36. 11-80 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 519 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 — — A10 A11 A12 A13 A14 A15 A16 A17 A18 See Section 11.6.5, “UPM DRAM Configuration Example,” for more details. MOTOROLA Chapter 11. Memory Controller 11-81 For More Information On This Product, Go to: www.freescale.com...
  • Page 520 LAST bit, will be taken from the first line of the pending UPM routine. 11-82 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 521 Figure 11-66 shows, the CSx and GPL1 states (C12 and F) and the WAEN value (C) are frozen until UPMWAIT is recognized as deasserted. WAEN is typically set before the line that contain UTA = 1. MOTOROLA Chapter 11. Memory Controller 11-83 For More Information On This Product, Go to: www.freescale.com...
  • Page 522 Consider the following DRAM organization: • Eight 64Mbit devices, each organized as 8M x 8bits • Each device has 12 row lines and 9 column lines. 11-84 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 523 • Timing of GPL[0–5]—In the MPC8xx’s UPM, the GPL lines could change on the positive edge of T2 or T3. In the MPC8280 these signals can change in the positive MOTOROLA Chapter 11. Memory Controller 11-85 For More Information On This Product, Go to: www.freescale.com...
  • Page 524 This section provides timing diagrams for various UPM configurations. 11-86 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 525 The OR and BR of the specific bank must be initialized according to the address mapping of the DRAM device used. The MS field should indicate the specific UPM selected to handle the cycle. The RAM array of the UPM can than be written through use of the MOTOROLA Chapter 11. Memory Controller 11-87 For More Information On This Product, Go to: www.freescale.com...
  • Page 526 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 Figure 11-68. Single-Beat Read Access to FPM DRAM 11-88 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 527 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+2 Figure 11-69. Single-Beat Write Access to FPM DRAM MOTOROLA Chapter 11. Memory Controller 11-89 For More Information On This Product, Go to: www.freescale.com...
  • Page 528 Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 11-70. Burst Read Access to FPM DRAM (No LOOP) 11-90 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 529 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 Figure 11-71. Burst Read Access to FPM DRAM (LOOP) MOTOROLA Chapter 11. Memory Controller 11-91 For More Information On This Product, Go to: www.freescale.com...
  • Page 530 Bit 30 last Bit 31 WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 Figure 11-72. Burst Write Access to FPM DRAM (No LOOP) 11-92 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 531 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 Figure 11-73. Refresh Cycle (CBR) to FPM DRAM MOTOROLA Chapter 11. Memory Controller 11-93 For More Information On This Product, Go to: www.freescale.com...
  • Page 532 • If GPL_4 is not used as an output, the performance for a page read access can be improved by setting MxMR[GPL_x4DIS]. The following example shows how the 11-94 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 533 MxMR[GPL_x4DIS] negative edge Burst inhibit device ORx[BI] The timing diagram in Figure 11-75 shows how the burst-read access shown in Figure 11-70 can be reduced. MOTOROLA Chapter 11. Memory Controller 11-95 For More Information On This Product, Go to: www.freescale.com...
  • Page 534 Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 Figure 11-75. FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN) 11-96 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 535 No write protect (R/W) BRx[WP] Refresh timer prescaler MPTPR 0x04 Refresh timer value (1024 refresh cycles) PURT[PURT] 0x07 Refresh timer enable MxMR[RFEN] Address multiplex size MxMR[AMx] 0b001 MOTOROLA Chapter 11. Memory Controller 11-97 For More Information On This Product, Go to: www.freescale.com...
  • Page 536 Memory System Interface Example Using UPM Table 11-44. EDO Connection Field Value Example (continued) Explanation Field Value Disable timer period MxMR[DSx] 0b10 Burst inhibit device ORx[BI] 11-98 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 537 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 RSS+3 RSS+4 Figure 11-77. Single-Beat Read Access to EDO DRAM MOTOROLA Chapter 11. Memory Controller 11-99 For More Information On This Product, Go to: www.freescale.com...
  • Page 538 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+2 WSS+3 Figure 11-78. Single-Beat Write Access to EDO DRAM 11-100 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 539 Bit 30 last Bit 31 WSS+1 WSS+2 REDO1 REDO2 REDO3 WSS+3 Figure 11-79. Single-Beat Write Access to EDO DRAM Using REDO to Insert Three Wait States MOTOROLA Chapter 11. Memory Controller 11-101 For More Information On This Product, Go to: www.freescale.com...
  • Page 540 Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 RBS+9 RBS+10 Figure 11-80. Burst Read Access to EDO DRAM 11-102 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 541 Bit 29 todt Bit 30 last Bit 31 WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 WBS+9 Figure 11-81. Burst Write Access to EDO DRAM MOTOROLA Chapter 11. Memory Controller 11-103 For More Information On This Product, Go to: www.freescale.com...
  • Page 542 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 PTS+3 PTS+4 Figure 11-82. Refresh Cycle (CBR) to EDO DRAM 11-104 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 543 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 Figure 11-83. Exception Cycle For EDO DRAM MOTOROLA Chapter 11. Memory Controller 11-105 For More Information On This Product, Go to: www.freescale.com...
  • Page 544 • The external termination solution (GPCM)—The core generates a read access from the slow device, which must generate the asynchronous GTA when it is ready. 11-106 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 545 • Memory address latch (ALE) to latch the 60x address for memory use • The address multiplex pin (GPL5/SDAMUX), which controls external multiplexing for DRAM and SDRAM devices MOTOROLA Chapter 11. Memory Controller 11-107 For More Information On This Product,...
  • Page 546 60x bus and keeps the address stable for the memory access. The memory controller asserts ALE only on the start of new memory controller access. Figure 11-84 shows the pipelined bus operation in 60x-compatible mode. 11-108 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 547 Figure 11-85 shows the 1-cycle delay for external master access. For systems that use the 60x bus with low frequency (33 MHz), the 1-cycle delay for external masters can be eliminated by setting BCR[EXDD]. MOTOROLA Chapter 11. Memory Controller 11-109 For More Information On This Product, Go to: www.freescale.com...
  • Page 548 SDAMUX, while the address latch is controlled by ALE. Also note that because this is a 64-bit port size SDRAM, BADDR is not needed. 11-110 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 549 MPC8280 External Master A[0–31] D[0–63] TT[0–4] TBST TSIZ[1–3] TSIZ[0–2] (pull down) TSIZ[0] PSDVAL (pull up) Arbitration signals Figure 11-86. External Master Configuration with SDRAM Device MOTOROLA Chapter 11. Memory Controller 11-111 For More Information On This Product, Go to: www.freescale.com...
  • Page 550 Freescale Semiconductor, Inc. External Master Support (60x-Compatible Mode) 11-112 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 551 Secondary (L2) Cache Support The MPC8280 has features to support an externally controlled secondary (L2) cache such as the Motorola MPC2605 integrated secondary cache for microprocessors that implement the PowerPC architecture. This chapter describes the MPC8280’s L2 cache interface—configurations, operation, programmable parameters, system requirements, and timing.
  • Page 552 Since every cacheable write operation goes to the L2 cache and to main memory, write operation latency is the same as an ordinary memory write transaction. In 12-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 553 MPC8280 can also support additional bus masters (60x or MPC8280-type) in write-through mode. Figure 12-2. shows a MPC8280 connected to a MPC2605 integrated L2 cache in write-through mode. MOTOROLA Chapter 12. Secondary (L2) Cache Support 12-3 For More Information On This Product,...
  • Page 554 • The MPC8280’s DP[0:7] signals are connected to the L2 cache’s DP[0:7] signals. • The L2’s TSIZ[0:2] signals are pulled down to always indicate 8-byte transaction size. • The L2’s A[29:31] signals are pulled down. 12-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 555 See Section 11.9, “External Master Support (60x-Compatible Mode),” for more information about external master types. Figure 12-3. shows a MPC8280 connected to an MPC2605 integrated L2 cache in ECC/Parity mode. MOTOROLA Chapter 12. Secondary (L2) Cache Support 12-5 For More Information On This Product,...
  • Page 556 The L2 cache interface parameters in the bus configuration register (BCR) control the configuration and operation of the MPC8280’s L2 interface. The parameters should be configured as follows: • BCR[EBM] = 1—MPC8280 in 60x-compatible mode. 12-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 557 ARTRY, it should not assert L2_HIT. For more information about the timing and behavior of the MPC2605 integrated L2 cache, refer to the MPC2605 data sheet. MOTOROLA Chapter 12. Secondary (L2) Cache Support 12-7 For More Information On This Product,...
  • Page 558 A0 & TBST& CI A1 & TBST Memc controls disabled active AACK MPC8280 DATA L2D = 0 L2 HIT Figure 12-4. Read Access with L2 Cache 12-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 559 The MPC8280’s implementation includes a TAP controller, a 4-bit instruction register, and two test registers (a 1-bit bypass register and a 475-bit boundary scan register). Figure 13-1 shows an overview of the MPC8280’s scan chain implementation. MOTOROLA Chapter 13. IEEE 1149.1 Test Access Port 13-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 560 The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is a synchronous state machine that controls the operation of the JTAG logic. 13-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 561 An IEEE-1149.1-compliant boundary-scan register has been included on the MPC8280 that can be connected between TDI and TDO when EXTEST or SAMPLE/PRELOAD instructions are selected. It is used for capturing signal pin data on MOTOROLA Chapter 13. IEEE 1149.1 Test Access Port 13-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 562 Figure 13-3. Output Pin Cell (O.Pin) To Next Cell Data to Input System Logic Shift DR Clock DR From Last Cell Figure 13-4. Observe-Only Input Pin Cell (I.Obs) 13-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 563 The MPC8280 JTAG implementation includes the public instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS) and also supports the CLAMP instruction. One additional public instruction (HI-Z) can be used to disable all device output drivers. The MOTOROLA Chapter 13. IEEE 1149.1 Test Access Port 13-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 564 TCK in the capture-DR controller state. Thus, the first bit to be shifted out after selecting the bypass register is always a logic zero. 13-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 565 This is done inside the chip by connecting TRST to PORESET TMS should remain logic high, so that the TAP controller does not leave the test-logic-reset state. MOTOROLA Chapter 13. IEEE 1149.1 Test Access Port 13-7 For More Information On This Product,...
  • Page 566 Freescale Semiconductor, Inc. Nonscan Chain Operation 13-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 567 16-bit or two 32-bit general-purpose timers. • Chapter 19, “SDMA Channels and IDMA Emulation,” describes the two physical serial DMA (SDMA) channels on the MPC8280. MOTOROLA Part IV. Communications Processor Module IV-1 For More Information On This Product,...
  • Page 568 • Chapter 32, “ATM AAL1 Circuit Emulation Service,” describes the implementation of circuit emulation service (CES) using ATM adaptation layer type 1 (AAL1) on the MPC8280. IV-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 569 This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC82xx Documentation Supporting documentation for the MPC8280 can be accessed through the world-wide web www.motorola.com/semiconductors. This documentation includes technical specifications, reference materials, and detailed applications notes.
  • Page 570 32-bit model. — Programming Environments for 32-Bit Implementations of the PowerPC Architecture, REV 3(Motorola order #: MPCFPE32B/AD) For a current list of documentation, refer to http://e-www.motorola.com. Conventions This document uses the following notational conventions: Bold entries in figures and tables showing registers and parameter Bold RAM should be initialized by the user.
  • Page 571 Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. MOTOROLA Part IV. Communications Processor Module IV-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 572 Enhanced Ethernet serial transceiver EPROM Erasable programmable read-only memory Free buffer pool FIFO First-in-first-out (buffer) General circuit interface GCRA Generic cell rate algorithm (leaky bucket) IV-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 573 Network interface card Network interface unit NMSI Nonmultiplexed serial interface Non-real time Open systems interconnection Peripheral component interconnect Protocol data unit Peak cell rate Physical layer MOTOROLA Part IV. Communications Processor Module IV-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 574 Unspecified bit rate UBR+ Unspecified bit rate with minimum cell rate guarantee UART Universal asynchronous receiver/transmitter User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter Wide area network IV-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 575 • Two multi-channel controllers (MCCs) (only MCC2 on the MPC8270 and the MPC8275) that together can handle up to 256 HDLC/transparent channels at 64 Kbps each, multiplexed on up to eight TDM interfaces MOTOROLA Chapter 14. Communications Processor Module Overview 14-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 576 — T1/CEPT lines — T3/E3 — Pulse code modulation (PCM) highway interface — ISDN primary rate — Motorola interchip digital link (IDL) — General circuit interface (GCI) — User-defined interfaces • Eight TC layers between the TDMs and FCC2 (MPC8280 only) •...
  • Page 577 E3 or E1’s E3 or E1’s ATM UART GSM mobile E1’s FEnet or ATM 10 M 10 M switching center Backbone HDLC HDLC MOTOROLA Chapter 14. Communications Processor Module Overview 14-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 578 “MPC8280 CPM Performance Evaluator,” which is located under “Application Software” on a device’s product page at www.motorola.com/semiconductors. 14.3.2 Features The following is a list of the CP’s important features.
  • Page 579 The CP also gives SDMA commands to the SDMA. The CP interfaces with the dual-port RAM for loading and storing data and for fetching instructions while running microcode from dual-port RAM. Figure 14-2 shows the CP block diagram. MOTOROLA Chapter 14. Communications Processor Module Overview 14-5 For More Information On This Product,...
  • Page 580 Decoder To all units Microcode Address Data Dual-Port RAM Address Data Interface 60x Bus Local Bus Figure 14-2. Communications Processor (CP) Block Diagram 14-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 581 Commands issued to the CPCR Emergency (from FCCs, MCCs, and SCCs) IDMA[1–4] emulation (default—option 1) USB receive USB transmit FCC1 receive FCC1 transmit MCC1 receive MOTOROLA Chapter 14. Communications Processor Module Overview 14-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 582 The CP has an option to execute microcode from a portion of user RAM located in the dual-port RAM. In this mode, the CP fetches instructions from both the dual-port RAM and its own private ROM. This mode allows Motorola to add new protocols or enhancements 14-8...
  • Page 583 Communications Processor (CP) to the MPC8280 in the form of RAM microcode packages. If preferred, the user can obtain binary microcode from Motorola and load it into the dual-port RAM. 14.3.7 RISC Controller Configuration Register (RCCR) The RISC controller configuration register (RCCR), as shown in Figure 14-3, configures the CP to run microcode from ROM or RAM and controls the CP’s internal timer.
  • Page 584 11 Reserved External interrupt enable. When EIE is set, DREQ1 acts as an external interrupt to the CP. Configure as instructed in the download process of a Motorola-supplied RAM microcode package. 0 DREQ1 cannot interrupt the CP. 1 DREQ1 will interrupt the CP.
  • Page 585 14.3.10 RISC Microcode Revision Number Associated with each version of CPM microcode, is a number (REV_NUM) that uniquely identifies that specific microcode. This number is hard-coded into the microcode which is MOTOROLA Chapter 14. Communications Processor Module Overview 14-11 For More Information On This Product,...
  • Page 586 — Reset 0000_0000_0000_0000 Addr 0x119C0 Field — OPCODE Reset 0000_0000_0000_0000 Addr 0x119C2 Only in USB. Otherwise reserved. Figure 14-6. CP Command Register (CPCR) 14-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 587 MCC channel number. Specifies the channel number in the case of an MCC command. In FCC protocols, this field contains the protocol code as follows: 0x00 HDLC, Transparent 0x0A ATM 0x0C Ethernet MOTOROLA Chapter 14. Communications Processor Module Overview 14-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 588 Set according to OPCODE[28-31]. If OPCODE is 1010, SBC must be 01110. Refer to Table 14-7. ATM functionality not available on the MPC8270. Not available on the MPC8270 and the MPC8275. Not available on the MPC8270. 14-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 589 — — — — VERSION CHANGE Undefined. Reserved for use by Motorola-supplied RAM microcodes. See FCC1 and FCC2 in SBC[6-10] in Table 13-6. Not available on the MPC8270. MPC8280 only. MOTOROLA Chapter 14. Communications Processor Module Overview 14-15 For More Information On This Product,...
  • Page 590 SET TIMER Set group address. Sets a bit in the hash table for the Ethernet logical group address recognition SET GROUP function. ADDRESS 14-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 591 14.4.3 Command Execution Latency The worst-case command execution latency is 200 clocks and the typical command execution latency is about 40 clocks. MOTOROLA Chapter 14. Communications Processor Module Overview 14-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 592 Slave address Slave data RISC Instruction address RISC instruction RISC trace buffer address Trace buffer data 32 Kbytes Figure 14-7. Internal RAM Block Diagram 14-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 593 • CP instruction fetcher (in case of microcode from RAM) • PPC 60x slave Figure 14-8 shows a memory map of the internal data RAM. The addresses refer to CPU address space. MOTOROLA Chapter 14. Communications Processor Module Overview 14-19 For More Information On This Product,...
  • Page 594 • Temporary storage between FCC FIFO and external memory for FCC data that is moved by BTM (from/to FCC FIFO) and SDMA (to/from external memory) 14-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 595 RAM can be located in the internal system RAM or in any unused parameter RAM, such as the area made available when a serial channel or sub-block is not being used. Microcode can be executed from the 32-Kbyte instruction RAM. MOTOROLA Chapter 14. Communications Processor Module Overview 14-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 596 The peripheral controllers (FCCs, SCCs, SMCs, MCCs, SPI, and I C) always use BDs for controlling buffers and their BD formats are all the same, as shown in Table 14-9. 14-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 597 The exact definition of the parameter RAM is contained in each protocol subsection describing a device that uses a parameter RAM. For example, the Ethernet parameter RAM is defined differently in some locations from the HDLC-specific parameter RAM. MOTOROLA Chapter 14. Communications Processor Module Overview 14-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 598 TIMERS 0x8AF0 REV_NUM 0x8AF2 Reserved 0x8AF4 Reserved 0x8AF8 RAND 0x8AFC C base 0x8AFE IDMA4 base 0x8B00 13-16 0x8C00 Reserved 1224 Offset from RAM_Base 14-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 599 Two areas of dual-port RAM, shown in Figure 14-10, are used for the RISC timer tables: • The RISC timer table parameter RAM • The RISC timer table entries MOTOROLA Chapter 14. Communications Processor Module Overview 14-25 For More Information On This Product,...
  • Page 600 15 has not been serviced, then TM_CNT would not be updated in that tick interval. Offset from timer base address (0x8AE0) 14-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 601 An interrupt is generated only if the RISC timer table bit is set in the SIU interrupt mask register; see Section 4.3.1.5, “SIU Interrupt Mask Registers (SIMR_H and SIMR_L).” MOTOROLA Chapter 14. Communications Processor Module Overview 14-27 For More Information On This Product, Go to: www.freescale.com...
  • Page 602 0x29E1_0008 to the CPCR. SET TIMER 9. Repeat the preceding two steps for each timer to be enabled or disabled. 14-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 603 CP decrements the count and checks for a timeout. If none occurs, the CP moves to the next timer. If a timeout occurs, the CP sets the corresponding MOTOROLA Chapter 14. Communications Processor Module Overview...
  • Page 604 NOTE General-purpose timers are up counters, but RISC timers are down counters. The user should take this under consideration when comparing timer counts. 14-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 605 TDM channels on SI1 are referred to as TDMa1, TDMb1, TDMc1, TDMd1; TDM channels on SI2 are TDMa2, TDMb2, TDMc2, TDMd2. MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-1 For More Information On This Product,...
  • Page 606 If the TSA is not used as intended, it can be used to generate complex wave forms on dedicated output pins. For instance, it can program these pins to implement stepper motor control or variable-duty cycle and period control on-the-fly. 15-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 607 — for FCCs transparent — for FCCs HDLC CPM Clock — for FCCs HDLC nibble mode CPM Clock — for all other serials MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 608 Figure 15-2 shows example TSA configurations ranging from the simplest to the most complex. 15-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 609 SMC1 SCC2 SCC2 TDM Tx 1 TDM Sync 1 TDM Clock TDM Rx Figure 15-2. Various Configurations of a Single TDM Channel MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 610 TXDx pins that supports a multiple-transmitter architecture occurs in the parallel I/O block. These strobes can also be used for generating output wave forms to support such applications as stepper-motor control. 15-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 611 The four TDMs are connected to four independent TDM interfaces. Figure 15-4 illustrates the connection between the TSA and the serial interfaces. The connection is made by MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-7 For More Information On This Product,...
  • Page 612 TDM. Programming the starting shadow bank address, described in Section 15.5.3, “SIx RAM Shadow Address Registers (SIxRSR),” 15-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 613 When the next frame sync arrives, the SI automatically exchanges the current-route RAM for the shadow RAM. See Section 15.4.5, “Static and Dynamic Routing.” MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-9 For More Information On This Product,...
  • Page 614 See Chapter 3, “Memory Map.” Figure 15-7. SIx RAM Entry Fields When MCC = 0, the SIx RAM entry fields function as described in Table 15-1. 15-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 615 11–13 Count. Indicates the number of bits/bytes (according to the BYT bit) that the routing and strobe select of this entry controls. 000 = 1 bit/byte; 111= 8 bits/bytes. MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-11 For More Information On This Product,...
  • Page 616 If the transmit and receive sections of the TDM do not use a common clock source, the SWTR feature can cause erratic behavior. Also note, this feature does not work with nibble operation. 15-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 617 Also note that, to avoid errors in switching to and from shadow SI RAM, the last entry in SI RAM should not be programmed to 1-bit resolution (i.e. CNT = 000 and BYT = 0). MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner...
  • Page 618 RAM. Then SIxMR[CRTx] can be used to instruct the SIx RAM to use the same clock and sync to simultaneously control both sets of SIx RAM entries. 15-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 619 RAM is the current-route RAM. The user can also externally connect one of the strobes to an interrupt pin to generate an interrupt on a particular SIx RAM entry starting or ending execution by the TSA. MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 620 SI RAMs of differing TDMx should not be interleaved. An example is shown in Figure 15-9. 15-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 621 Route CSRTb=0 L1RCLKa L1RCLKb Framing Signals: L1RSYNCa L1RSYNCb Figure 15-9. Example: SIx RAM Dynamic Changes, TDMa and b, Same SIx RAM Size MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 622 (with SIx RAM) to support any or all of the ISDN channels independently when in IDL or GCI mode. Any extra serial channel can then be used for other purposes. 15-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 623 This mode is used to accomplish loopback testing of the entire TDM without affecting the external serial lines. Note: In modes 01, 10, and 11, the receive and transmit clocks should be identical. MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 624 See Figure 15-13, Figure 15-14, Figure 15-15, and Figure 15-16. 0 Falling edge. Use for IDL and GCI. 1 Rising edge. 15-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 625 No Delay from Sync Latch to First Bit of Frame Figure 15-13. No Delay from Sync to Data (xFSD = 00) Figure 15-14 shows the effects of changing FE when CE = 1 with a 1-bit frame sync delay. MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 626 Both the FE Settings (On Bit-0) Rx Sampled Here Figure 15-15. Falling Edge (FE) Effect When CE = 0 and xFSD = 01 15-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 627 L1ST and Data Bit-0 is Driven L1ST from Clock Low. (On Bit-0) Figure 15-16. Falling Edge (FE) Effect When CE = 1 and xFSD = 00 MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 628 The SIx RAM shadow address registers (SIxRSR), shown in Figure 15-18, define the starting addresses of the shadow section in the SIx RAM for each of the TDM channels. 15-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 629 Field CSRRA CSRTA CSRRB CSRTB CSRRC CSRTC CSRRD CSRTD Reset 0000_0000 Addr 11B2A (SI1CMDR), 11B4A (SI2CMDR) Figure 15-19. SI Command Register (SIxCMDR) MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-25 For More Information On This Product, Go to: www.freescale.com...
  • Page 630 The IDL interface is a full-duplex ISDN interface used to connect a physical layer device to the MPC8280. The MPC8280 supports both the basic and primary rate of the IDL bus. 15-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 631 The SPI is used to send initialization commands and periodically check status from the S/T transceiver. The SMC connected to the terminal is configured for UART. MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-27 For More Information On This Product, Go to: www.freescale.com...
  • Page 632 IDL grant permission to transmit on the D Channel; input to the MPC8280 on the L1TSYNCx pin. Note: x = a, b, c, and d for TDMa, TDMb, TDMc, and TDMd (for SI1 and SI2). 15-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 633 IDL definition when it was concluded that the IDL control channel would be out-of-band. These functions were defined as a subset of the Motorola SPI format called serial control port (SCP). To implement the A and M bits as originally defined, program the TSA to access these bits and route them transparently to an SCC or SMC.
  • Page 634 IDL, 8 or 10 bits, are implemented by simply modifying the SIx RAM programming. In both cases, L1GRx is sampled while L1TSYNCx is asserted and transferred to the D-channel SCC as a grant indication. 15-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 635 13. Set PPARB[17]. Configures L1RQa. 14. Clear PSORB[17]. Configures L1RQa. 15. Set PDIRB[17]. Configures L1RQa. 16. Set PPARD[13]. Configures L1ST1. 17. Clear PSORD[13]. Configures L1ST1. MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-31 For More Information On This Product, Go to: www.freescale.com...
  • Page 636 L1RCLKx divided by 2; otherwise, it is simply a 1× output of the L1RCLKx signal. Note: x = a, b, c, and d for TDMa, TDMb, TDMc, and TDMd (for SI1 and SI2). 15-32 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 637 4 of C/I channel 2 to logic high. The MPC8280 then aborts its transmission and retransmits the frame when this bit is set again. This procedure is automatically handled for the first two buffers of a frame. MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-33 For More Information On This Product, Go to: www.freescale.com...
  • Page 638 SIx RAM to 0b0111 for an internal assertion of a strobe on this bit. This bit is sampled by the SI and transferred to 15-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 639 L1RSYNCa. 8. Set PDIRA[9]. Configures L1TXDa[0]. 9. Set PODRA[9]. Configures L1TXDa[0] to an open-drain output. 10. Set PPARC[30,31]. Configures L1TCLKa and L1RCLKa. MOTOROLA Chapter 15. Serial Interface with Time-Slot Assigner 15-35 For More Information On This Product, Go to: www.freescale.com...
  • Page 640 18. SI1GMR = 0x11. Enable TDMa (one static TDM), STZ for TDMa. 19. SI1CMDR is not used. 20. SI1STR does not need to be read. 21. Enable the SCC1, SCC2, SMC1 and SMC2. 15-36 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 641 CMX to connect a serial device to the SI, the CMX connects that serial device to both SIs. Programming both SIs to use one serial device in the same time slot causes erratic behavior. MOTOROLA Chapter 16. CPM Multiplexing 16-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 642 • FCC1 can also be connected to an 8- or 16-bit ATM UTOPIA level-2 interface (not on the MPC8270). • FCC2 can also be connected also to an 8-bit ATM UTOPIA level-2 interface (not on the MPC8270). 16-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 643 FCC2 can also be connected to an 8-bit UTOPIA level-2 interface. Each SCC or SMC can be connected to the eight TDMs or to its own set of pins. Once connections are made to the TSA, the exact routing decisions are made in the SIx RAMs. MOTOROLA Chapter 16. CPM Multiplexing 16-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 644 This configuration leaves additional pins for other functions and minimizes potential skew between multiple clock sources. 16-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 645 • Only four of the twenty sources can be connected to any given FCC or SCC receiver or transmitter. • The SMC transmitter and receiver share the same clock source when connected to the NMSI. MOTOROLA Chapter 16. CPM Multiplexing 16-5 For More Information On This Product,...
  • Page 646 TDMA2 Tx TDMB2 Rx TDMB2 Tx TDMC2 Rx TDMC2 Tx TDMD2 Rx V TDMD2 Tx SMC1 Rx SMC1 Tx SMC2 Rx SMC2 Tx 16-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 647 0 This address input pin is used by FCC2 in slave mode. 1 This address input pin is used by FCC1 in slave mode. — Reserved, should be cleared. MOTOROLA Chapter 16. CPM Multiplexing 16-7 For More Information On This Product,...
  • Page 648 FCC1 and three are always connected to FCC2. The user decides which FCC uses the remaining two pins by programming CMXUAR[MADx]. See Figure 16-5. 16-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 649 NOTE: To use FCC2 as shown, connect the FCC2 address bits reversed with respect to the pinout address indexes. PHY address pins with no pin connection should be connected to GND. Figure 16-6. Connection of the Slave Address MOTOROLA Chapter 16. CPM Multiplexing 16-9 For More Information On This Product,...
  • Page 650 FCC1 and FCC2 receive multi-PHY addresses. The same diagram applies to the transmit multi-PHY bus using different dedicated parallel I/O pins. 16-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 651 16.4.2 CMX SI1 Clock Route Register (CMXSI1CR) The CMX SI1 clock route register (CMXSI1CR), displayed in Figure 16-8, defines the connection of SI1 to the clock sources that can be input from the bank of clocks. MOTOROLA Chapter 16. CPM Multiplexing 16-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 652 The CMX SI2 clock route register (CMXSI2CR), seen in Figure 16-9, defines the connection of SI2 to the clock sources that can be input from the bank of clocks. 16-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 653 16.4.4 CMX FCC Clock Route Register (CMXFCR) The CMX FCC clock route register (CMXFCR), shown in Figure 16-10, defines the connection of the FCCs to the TSA and to the clock sources from the bank of clocks. MOTOROLA Chapter 16. CPM Multiplexing 16-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 654 100 FCC1 transmit clock is CLK9. 101 FCC1 transmit clock is CLK10. 110 FCC1 transmit clock is CLK11. 111 FCC1 transmit clock is CLK12. 16-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 655 011 FCC3 receive clock is BRG8. 100 FCC3 receive clock is CLK13. 101 FCC3 receive clock is CLK14. 110 FCC3 receive clock is CLK15. 111 FCC3 receive clock is CLK16. MOTOROLA Chapter 16. CPM Multiplexing 16-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 656 The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O control register. 1 SCC1 is connected to TSA of the SIs. The NMSIx pins are available for other purposes. 16-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 657 0 SCC3 transmitter does not support the grant mechanism. The grant is always asserted internally. 1 SCC3 transmitter supports the grant mechanism as determined by the GMx bit of a serial device channel. MOTOROLA Chapter 16. CPM Multiplexing 16-17 For More Information On This Product,...
  • Page 658 100 SCC4 transmit clock is CLK5. 101 SCC4 transmit clock is CLK6. 110 SCC4 transmit clock is CLK7. 111 SCC4 transmit clock is CLK8 16-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 659 00 SMC2 transmit and receive clocks are BRG2. 01 SMC2 transmit and receive clocks are BRG8. 10 SMC2 transmit and receive clocks are CLK19. 11 SMC2 transmit and receive clocks are CLK20. MOTOROLA Chapter 16. CPM Multiplexing 16-19 For More Information On This Product,...
  • Page 660 Freescale Semiconductor, Inc. CMX Registers 16-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 661 CLK Pin y Source 12-Bit Counter 1 or 16 Bank of Clocks 1–4,096 BRGCLK Autobaud RXDn Control BRGn Figure 17-1. Baud-Rate Generator (BRG) Block Diagram MOTOROLA Chapter 17. Baud-Rate Generators (BRGs) 17-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 662 BRG clock cycle (no spikes occur on the BRGO output clock). BRGC can be changed on-the-fly; however, two changes should not occur within a time equal to two source clock periods. 17-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 663 0 Normal operation of the BRG. 1 When RXD goes low, the BRG determines the length of the start bit and synchronizes the BRG to the actual baud rate. MOTOROLA Chapter 17. Baud-Rate Generators (BRGs) 17-3 For More Information On This Product,...
  • Page 664 (for example, 56,600 may result rather than 57,600). An interrupt can be enabled in the 17-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 665 Table 17-3 lists typical bit rates of asynchronous communication. Note that here the internal clock rate is assumed to be 16× the baud rate; that is, GSMRx_L[TDCR] = GSMRx_L[RDCR] = 0b10. MOTOROLA Chapter 17. Baud-Rate Generators (BRGs) 17-5 For More Information On This Product,...
  • Page 666 For example, to get a rate of 64 kbps, the system clock can be 24.96 MHz, BRGCx[DIV16] = 0, and BRGCx[CD] = 389. 17-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 667 Capture Register TOUT4 Timer1 Timer2 Timer3 Timer4 Figure 18-1. Timer Block Diagram Pin assignments for TINx, TGATEx, and TOUTx are described in Section 41.5, “Ports Tables.” MOTOROLA Chapter 18. Timers 18-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 668 (TOUT1–TOUT4) when the reference value is reached (selected by the corresponding TMR[OM]). This signal can be an active-low pulse or a toggle of the current output. The 18-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 669 Because the decision to cascade timers is made independently, the user can select two 16-bit timers or one 32-bit timer. TGCR is used to put the timers into cascaded mode, as shown in Figure 18-2. MOTOROLA Chapter 18. Timers 18-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 670 Description CAS2 Cascade timers. 0 Normal operation. 1 Timers 1 and 2 cascade to form a 32-bit timer. — Reserved, should be cleared. 18-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 671 Table 18-2. TGCR2 Field Descriptions Name Description CAS4 Cascade timers. 0 Normal operation. 1 Timers 3 and 4 cascades to form a 32-bit timer. — Reserved, should be cleared. MOTOROLA Chapter 18. Timers 18-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 672 Only TGCR[RST] can be modified at any time. Field ICLK Reset 0000_0000_0000_0000 Addr 0x10D90 (TMR1); 0x10D92 (TMR2); 0x10DA0 (TMR3); 0x10DA2 (TMR4) Figure 18-5. Timer Mode Registers (TMR1–TMR4) 18-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 673 The reference value is not reached until TCNx increments to equal the timeout reference value. Field Timeout reference value Reset 0xFFFF Addr 0x10D94 (TRR1), 0x10D96 (TRR2), 0x10DA4 (TRR3), 0x10DA6 (TRR4) Figure 18-6. Timer Reference Registers (TRR1–TRR4) MOTOROLA Chapter 18. Timers 18-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 674 TMRx[CE]. TER1–TER4 can be read at any time. Writing ones clears event bits; writing zeros has no effect. Both event bits must be cleared before the timer negates the interrupt. 18-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 675 Output reference event. The counter has reached the TRR value. TMR[ORI] is used to enable the interrupt request caused by this event. Capture event. The counter value has been latched into the TCR. TMR[CE] is used to enable generation of this event. MOTOROLA Chapter 18. Timers 18-9 For More Information On This Product,...
  • Page 676 Freescale Semiconductor, Inc. General-Purpose Timer Units 18-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 677 Internal 60x Bus Core Dual-Port External SDMA Local External 2 MCCs 3 FCCs 4 SCCs 2 SMCs Figure 19-1. SDMA Data Paths MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 678 60x system bus. The SDMA channel can be assigned big-endian (Motorola) or little-endian format for accessing buffer data. These features are programmed in the receive and transmit registers...
  • Page 679 Figure 19-3. SDMA Status Register (SDSR) Table 19-1 describes SDSR fields. Table 19-1. SDSR Field Descriptions Bits Name Description 0–5 — Reserved, should be cleared. MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 680 PDTEM is for SDMA transfer errors on the 60x bus, and LDTEM is for errors on the local/PCI bus. Both registers are undefined at reset. See Figure 19-4. 19-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 681 The single-address mode (fly-by mode) gives the highest performance, allowing data to be transferred between memory and a peripheral in a single bus transaction. The chip-select and wait-state generation logic on the MPC8280 can be used with the IDMA. MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 682 (of programmable size) in the dual-port RAM (note that the IDMA cannot burst to or from the dual-port RAM). An efficient data-packing algorithm bursts data 19-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 683 Source/destination transfer size. These parameters determine the access sizes in which the source/destination is accessed in steady state of work. At least one of these values (DTS/STS) must be initialized to the value of SS_MAX. MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 684 1–31 bytes written in single accesses. The last transfers, read/write or both can be accompanied with DONE assertion, if programmed. 19-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 685 Because at least one of the transfer sizes (STS or DTS) equals SS_MAX, every DREQ assertion causes one transfer to the smaller (in STS/DTS terms) bus. If STS = DTS, asserting DREQ triggers one read transfer automatically followed by one write transfer. MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-9 For More Information On This Product, Go to: www.freescale.com...
  • Page 686 This allows the IDMA to access a FIFO buffer the same way it does peripherals. DCM[S/D] determines whether the peripheral is the source or destination. 19-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 687 Transfers.” STS is initialized to SS_MAX and DTS is initialized to the peripheral port size. The first DREQ peripheral assertion triggers a read of SS_MAX (or more in the first phase) bytes from the memory into the internal transfer buffer, automatically followed by a write MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 688 Thus, data is transferred from memory to a peripheral in one data phase instead of two, increasing throughput. 19-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 689 • The 60x bus traffic is relatively low. Large bursts are preferred as long as they do not overload the bus. Setting DTS to 63*32 (SS_MAX) might be enough, but are too large for most of the systems because the dual-port RAM buffer would be written in MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 690 19.7 IDMA Interface Signals Each IDMA has three dedicated handshake control signals for transfers involving an external peripheral device: DMA request (DREQ[1–4]), DMA acknowledge (DACK[1–4]) 19-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 691 Controller Configuration Register (RCCR).” DREQx is sampled at each rising edge of the clock to determine when a valid request is asserted by the device. MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-15 For More Information On This Product,...
  • Page 692 DONE is ignored if it is asserted externally during internal request mode (DCM[ERM] = 0). DONE must asserted externally during memory-to-memory transfers if external request mode is enabled (DCM[ERM] = 1). 19-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 693 19.8.1 Auto Buffer and Buffer Chaining The core processor should initialize the IDMA BD table with the appropriate buffer handling mode, source address, destination address, and block length. See Figure 19-7. MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 694 Each IDMAx channel parameter table can be placed at any 64-byte aligned address in the dual-port RAM’s general-purpose area (banks 1–8, 11 and 12). The CP accesses each 19-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 695 – STS must be divided by 32 to enable bursts during the steady-state phase. • See Table 19-7 for memory-to-memory valid STS values. 0x10 DPR_OUT_PTR Hword Read pointer inside the internal buffer. MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-19 For More Information On This Product,...
  • Page 696 RAM, that controls the operation modes of the IDMA channel. As are all other IDMA parameters, the DCM is undefined at reset. Field — — DMA_WRAP SINC DINC ERM Reset — Figure 19-8. DCM Parameters 19-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 697 1 CP increments the destination pointer (D_PTR) with the number of bytes transferred in the destination write transaction. Used for memory-to-memory and memory-to-peripheral transfers. In fly-by mode, DINC should equal SINC. MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-21 For More Information On This Product,...
  • Page 698 Write to memory: in one transfer or more until internal buffer empties. On the bus: singles or bursts, depends on DTS 19-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 699 31 * 32 31 * 32, 32 1, 31 1024 31 * 32 31 * 32, 32 31 * 32 1, 31 MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 700 The transfer parameters STS, DTS, SS_MAX, and DMA_WRAP determine the amount of data transferred for each command issued. Using large internal IDMA START IDMA 19-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 701 19.8.5 IDMA BDs Source addresses, destination addresses, and byte counts are presented to the CP using the special IDMA BDs. The CP reads the BDs, programs the SDMA channel, and notifies the MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-25 For More Information On This Product, Go to: www.freescale.com...
  • Page 702 START IDMA This bit should be set only in buffer chaining mode (CM bit 6 = 0). — Reserved, should be cleared. 19-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 703 1 Snooping is activated for write transactions to the destination. In fly-by mode, should be the same as SGBL. 12-13 Destination byte ordering: 01 Munged little Endian. 1x Big endian (Motorola). 00 Reserved In fly-by mode, should be the same as SBO. — Reserved, should be cleared.
  • Page 704 IDSR[EDN] event is set and an interrupt is generated to the core, if enabled. • command was issued. STOP IDMA • The channel has finished a transfer of a BD with the last bit (L) set. 19-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 705 MPC8280) is used, it is easy to make provisions for a bus master to detect and respond to errors during a bus transaction. The IDMA recognizes the same bus exceptions as the core, reset and transfer error, as described in Table 19-11. MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-29 For More Information On This Product, Go to: www.freescale.com...
  • Page 706 • The default is the value that is seen by the IDMA channel on the pin (input or inout mode only—PDIR[PN] = 0) if a PSORx register bit is set to the complement value 19-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 707 In the example in Table 19-15, the IDMA2 channel reads 8 bytes per DREQ assertion from a fixed address peripheral located on the 60x bus into the internal buffer. When there is MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation...
  • Page 708 IDMA2 configuration: DREQ is edge low-to-high. DONE is high-to-low. Request priority is higher than the SCCs. 88FE = 0x0300 IDMA2_BASE points to 0x0300 where the parameter table base address is located for IDMA2. 19-32 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 709 The current BD pointer is set to the BD table base address (aligned 16 -bits[3–0]=0000). 0x0030 STS = 0x0004 Transfers from memory to peripheral are always 4 bytes long (60x singles). MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-33 For More Information On This Product,...
  • Page 710 The transfers to memory on the 60x bus are shorter, arbitration priority is low, and the internal request priority of IDMA1 is lowest to prevent other device starvation on the 60x bus, which is loaded. 19-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 711 IDMA1 configuration: Internal request priority is the lowest. 87FE=0x0100 IDMA1_BASE points to 0x0100 where the parameter table base address is located for IDMA1. MOTOROLA Chapter 19. SDMA Channels and IDMA Emulation 19-35 For More Information On This Product, Go to: www.freescale.com...
  • Page 712 : after all data in internal buffer is written to the 60x bus, BD is closed and SC interrupt is set. Channel is STOP IDMA stopped until command is issued. START IDMA 19-36 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 713 SCC internal clock can run at 12.5 MHz in a 50-MHz system.) However, an SCC’s ability to support a sustained bit stream depends on the protocol as well as other factors. MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 714 (UART), AppleTalk/LocalTalk, and totally transparent protocols • Supports 10-Mbps Ethernet/IEEE 802.3 (half- or full-duplex) on all SCCs • Additional protocols supported through Motorola-supplied RAM microcodes: Profibus and Signaling System#7 (SS7) • DPLL circuitry for clock recovery with NRZ, NRZI, FM0, FM1, Manchester, and...
  • Page 715 TFL RFW TXSY SYNL RTSM RSYN Reset 0000_0000_0000_0000 Addr 0x11A06 (GSMR1); 0x11A26 (GSMR2); 0x11A46 (GSMR3); 0x11A66 (GSMR4) Figure 20-2. GSMR_H—General SCC Mode Register (High Order) MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 716 1 The Tx FIFO is 1 byte. This option is used with character-oriented protocols, such as UART, to ensure a minimum FIFO latency at the expense of performance. 20-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 717 RSYN Receive synchronization timing (totally transparent mode only). 0 Normal operation. 1 If CDS = 1 CD should be asserted on the second bit of the Rx frame rather than on the first. MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-5 For More Information On This Product,...
  • Page 718 Note: Recommended for Ethernet, HDLC, and transparent operation when clock rates exceed 8 MHz to improve data setup time for the external transceiver. 20-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 719 0 Default operation. TXD is encoded only when data is sent, including the preamble and opening and closing flags/syncs. When no data is available to send, the signal is driven high. 1 TXD is always encoded, even when idles are sent. MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 720 “Reconfiguring the SCCs,” describes how to disable/enable an SCC. Note that other tools, including commands and the E bit of the Rx BD, data provide the ENTER HUNT MODE CLOSE RXBD capability to control the receiver. 20-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 721 • BISYNC and transparent—DSR should be programmed with the sync pattern. • Ethernet—DSR should be programmed with 0xD555. • HDLC—At reset, DSR defaults to 0x7E7E (two HDLC flags), so it does not need to be written. MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-9 For More Information On This Product,...
  • Page 722 New TxBDs are processed in order. The first bit of the frame is typically clocked out 5-6 bit times after TOD is set. 1–15 — Reserved, should be cleared. 20-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 723 BD table. The CPM does assume, however, that the unlinked buffers are provided by the core in time to be sent or received; otherwise, an MOTOROLA Chapter 20. Serial Communications Controllers (SCCs)
  • Page 724 BD; it continues until the buffer is full or an event, such as an error or end-of-frame detection, occurs. The 20-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 725 Rx function code. See Section 20.3.2, “Function Code Registers (RFCR and TFCR).” 0x05 TFCR Byte Tx function code. See Section 20.3.2, “Function Code Registers (RFCR and TFCR).” MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 726 From SCC base. See Section 20.3.1, “SCC Base Addresses.” These parameters need not be accessed for normal operation but may be helpful for debugging. For CP use only 20-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 727 Table 20-6 describes RFCRx/TFCRx fields. Table 20-6. RFCRx /TFCRx Field Descriptions Bits Name Description 0–1 — Reserved, should be cleared. Global 0 Snooping disabled. 1 Snooping enabled. MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 728 Follow these steps to handle an SCC interrupt: 1. When an interrupt occurs, read SCCE to determine the interrupt sources and clear those SCCE bits (in most cases). 20-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 729 An SCC should be disabled and reenabled after any dynamic change to its parallel I/O ports or serial channel physical interface configuration. A full reset can also be implemented using CPCR[RST]. MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 730 CTS is asserted. Figure 20-10 shows that the delay between CTS and the data can be approximately 0.5 to 1 bit times or no delay, depending on GSMR_H[CTSS]. 20-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 731 GSMR_H[CTSS] is zero, the SCC must sample CTS before a CTS lost is recognized; otherwise, the negation of CTS immediately causes the CTS lost condition. See Figure 20-11. MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-19 For More Information On This Product,...
  • Page 732 CD is sampled on the rising Rx clock edge before data is received. If GSMR_H[CDS] is 1, CD transitions cause data to be immediately gated into the receiver. 20-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 733 • If CTS is already asserted when RTS is asserted, transmission begins in two additional bit times. • If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 0, transmission begins in three additional bit times. MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-21 For More Information On This Product,...
  • Page 734 Receiver RINV Hunting 1x Mode Decoded Data HSRCLK RINV SCCR Data RENC ≠ NRZI 1x Mode HSRCLK Figure 20-13. DPLL Receiver Block Diagram 20-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 735 Table 20-8. When transmission occurs, the SCC can generate preamble patterns, as programmed in GSMR_L[TPP, TPL]. MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-23 For More Information On This Product,...
  • Page 736 Each SCC contains a DPLL unit that can be programmed to encode and decode the SCC data as NRZ, NRZI Mark, NRZI Space, FM0, FM1, Manchester, and Differential Manchester. Figure 20-15 shows the different encoding methods. 20-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 737 A zero is represented by a transition at the center of the bit with the same polarity from the transition at the center of the preceding bit. MOTOROLA Chapter 20. Serial Communications Controllers (SCCs)
  • Page 738 2. Modify SCC Rx parameters or parameter RAM. To switch protocols or restore Rx parameters to their initial state, issue an command. INIT RX PARAMETERS 20-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 739 3. Set GSMR_L[ENT, ENR] to enable the SCC with the new protocol. 20.3.8 Saving Power To save power when not in use, an SCC can be disabled by clearing GSMR_L[ENT, ENR]. MOTOROLA Chapter 20. Serial Communications Controllers (SCCs) 20-27 For More Information On This Product,...
  • Page 740 Freescale Semiconductor, Inc. SCC Parameter RAM 20-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 741 RS-232 links. Even synchronous protocols like HDLC are sometimes defined to run over asynchronous links. The Profibus standard extends UART protocol to include LAN-oriented features such as token passing. MOTOROLA Chapter 21. SCC UART Mode 21-1 For More Information On This Product,...
  • Page 742 • Programmable data length (5–8 bits) • Programmable fractional stop bit lengths (from 9/16 to 2 bits) in transmission • Capable of reception without a stop bit 21-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 743 In synchronous mode, the controller uses a 1× data clock for timing. The receive shift register receives incoming data on RXDx synchronous with the clock. The bit length and format of the serial character are defined by the control bits in the PSMR in the same way MOTOROLA Chapter 21. SCC UART Mode 21-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 744 In this case, program the lower order 0x4A UADDR2 Hword bytes of UADDR1 and UADDR2 with the two preferred addresses. 0x4C RTEMP Hword Temp storage 21-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 745 For character-based transfers, each character is sent with stop bits and parity and received into separate 1-byte buffers. A maskable interrupt is generated when each buffer is received. MOTOROLA Chapter 21. SCC UART Mode 21-5 For More Information On This Product,...
  • Page 746 Resets the transmit parameters in the parameter RAM. Issue only when the transmitter is disabled. Note INIT TX that resets both Tx and Rx parameters. PARAMETERS INIT TX AND RX PARAMETERS 21-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 747 • Manual multidrop mode—The controller receives all characters. An address character is always written to a new buffer and can be followed by data characters. User software performs the address comparison. MOTOROLA Chapter 21. SCC UART Mode 21-7 For More Information On This Product,...
  • Page 748 The 16-bit entries in the control character table support control character recognition. Each entry consists of the control character, a valid bit (end of table), and a reject bit. See Figure 21-3. 21-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 749 RCCR and generates a maskable interrupt. If the core does not process the interrupt and read RCCR before a new control character arrives, the previous control character is overwritten. MOTOROLA Chapter 21. SCC UART Mode 21-9 For More Information On This Product,...
  • Page 750 Interrupt. If this bit is set, transmission completion is flagged in the event register (SCCE[TX] is set), triggering a maskable interrupt to the core. 21-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 751 FSB can be modified at any time. If two stop bits are sent, only the second is affected. Idle characters are always sent as full-length characters MOTOROLA Chapter 21. SCC UART Mode 21-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 752 BDs, the error counters, and the SCCE. Modem interface lines can be monitored by the port C pins. Transmission errors are described in Table 21-7. 21-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 753 Rx buffer, sets RxBD[BR], and sets SCCE[RX], which can generate an interrupt if not masked. If PSMR[RZS] = 1 when the UART is in synchronous mode, a break sequence is detected after two successive break characters are received. MOTOROLA Chapter 21. SCC UART Mode 21-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 754 11 Automatic multidrop mode. The CPM compares the address of an incoming address character with UADDRx parameter RAM values; subsequent data is accepted only if a match occurs. 21-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 755 11 High parity (mark parity). The transmitter sends a one in the parity bit position. If the receiver does not read a 1 in the parity bit, a parity error is reported. MOTOROLA Chapter 21. SCC UART Mode 21-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 756 • An address character is received in multidrop mode. The address character is written to the next buffer for a software comparison. Figure 21-7 shows an example of how RxBDs are used in receiving. 21-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 757 5 Characters Long Idle Period Characters Received by UART Fourth Character Present Time has Framing Error! Time Figure 21-7. SCC UART Receiving using RxBDs MOTOROLA Chapter 21. SCC UART Mode 21-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 758 PSMR[UM]. After an address match, AM identifies which user-defined address character was matched. 0 The address matched the value in UADDR2. 1 The address matched the value in UADDR1. 21-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 759 1 Last BD in the table. After this buffer is used, the CPM sends data using the BD pointed to by TBASE. The number of TxBDs in this table is determined only by the W bit and space constraints of the dual-port RAM. MOTOROLA Chapter 21. SCC UART Mode 21-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 760 SCCE. Setting a mask bit enables the corresponding SCCE interrupt; clearing a bit masks it. Figure 21-10 shows example interrupts that can be generated by the SCC UART controller. 21-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 761 0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4) 0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4) Figure 21-11. SCC UART Event Register (SCCE) and Mask Register (SCCM) MOTOROLA Chapter 21. SCC UART Mode 21-21 For More Information On This Product,...
  • Page 762 RXD. Field — Reset 0000_0000_0000_0000 Addr 0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4) Figure 21-12. SCC Status Register for UART Mode (SCCS) 21-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 763 11. Set BRKCR to 0x0001 so commands send only one break STOP TRANSMIT character. 12. Clear PAREC, FRMEC, NOSEC, and BRKEC in parameter RAM. MOTOROLA Chapter 21. SCC UART Mode 21-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 764 For flow control, each device can transmit XON and XOFF characters, which are not part of the program being uploaded or downloaded. 21-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 765 TxBD table; transmission can be paused when an XOFF character is received. This scheme minimizes the number of interrupts the core receives (one per S-record) and relieves it from continually scanning for control characters. MOTOROLA Chapter 21. SCC UART Mode 21-25 For More Information On This Product, Go to: www.freescale.com...
  • Page 766 Freescale Semiconductor, Inc. S-Records Loader Application 21-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 767 HDLC controller, and consists of separate transmit and receive sections whose operations are asynchronous with the core and can either be synchronous or asynchronous with respect to other SCCs. MOTOROLA Chapter 22. SCC HDLC Mode 22-1 For More Information On This Product,...
  • Page 768 STOP TRANSMIT linked buffers or to support efficient error handling. When the SCC receives a STOP 22-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 769 Rx FIFO delay. 22.4 SCC HDLC Parameter RAM For HDLC mode, the protocol-specific area of the SCC parameter RAM is mapped as in Table 22-1. MOTOROLA Chapter 22. SCC HDLC Mode 22-3 For More Information On This Product,...
  • Page 770 HMASK bits. See Figure 22-2. 0x58 Hword Temporary storage. 0x5A TMP_MB Hword Temporary storage. From SCC base. See Section 20.3.1, “SCC Base Addresses.” 22-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 771 HDLC Tx parameters and Tx BDs can then be updated. TBPTR points to the next TxBD. Transmission TRANSMIT begins once TxBD[R] of the next BD is set and a command is issued. RESTART TRANSMIT MOTOROLA Chapter 22. SCC HDLC Mode 22-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 772 36 bytes for SCC or 20 bytes for SCC. The channel also increments the retransmission counter RETRC in the parameter RAM. 22-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 773 Field — FSE DRT BUS BRM MFF — Reset Addr 0x11A08 (PSMR1); 0x11A28 (PSMR2); 0x11A48 (PSMR3); 0x11A68 (PSMR4) Figure 22-3. HDLC Mode Register (PSMR) MOTOROLA Chapter 22. SCC HDLC Mode 22-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 774 This can improve performance of HDLC transmissions of small back-to-back frames or when the number of flags between frames should be limited. 13–15 — Reserved, should be cleared. 22-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 775 Note that when a DPLL error occurs, the frame closes and error checking halts. — Reserved, should be cleared. MOTOROLA Chapter 22. SCC HDLC Mode 22-9 For More Information On This Product,...
  • Page 776 2 or 4 bytes for CRC. Figure 22-5 shows an example of how RxBDs are used in receiving. 22-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 777 F = Flag A = Address byte C = Control byte I = Information byte CR = CRC Byte Figure 22-5. SCC HDLC Receiving Using RxBDs MOTOROLA Chapter 22. SCC HDLC Mode 22-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 778 If data from more than one buffer is currently in the FIFO when this error occurs, the HDLC writes CT in the current BD after sending the buffer. 22-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 779 Reserved, should be cleared. Refer to note 1 below. Tx error. Indicates an error (CTS lost or underrun) has occurred on the transmitter channel. This event is not maskable via the TxBD[I] bit. MOTOROLA Chapter 22. SCC HDLC Mode 22-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 780 Reserved bits in the SCCE should not be masked in the SCCM register. Figure 22-8 shows interrupts that can be generated using the HDLC protocol. 22-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 781 RXD. The real-time status of CTS and CD are part of the port C parallel I/O. Field — Reset 0000_0000 Addr 0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4) Figure 22-9. CC HDLC Status Register (SCCS) MOTOROLA Chapter 22. SCC HDLC Mode 22-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 782 TxBD tables in dual-port RAM. Assuming one RxBD at the start of dual-port RAM and one TxBD following it, write RBASE with 0x0000 and TBASE with 0x0008. 22-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 783 CCITT-CRC, and prevent multiple frames in the FIFO. 26. Write 0x00000030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional write ensures that ENT and ENR are enabled last. MOTOROLA Chapter 22. SCC HDLC Mode 22-17 For More Information On This Product,...
  • Page 784 To determine whether a channel is clear, the S/T interface device looks at an echo bit on the line designed to echo the last bit sent on the D channel. Depending on the class of terminal 22-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 785 Figure 22-10 shows the most common HDLC bus LAN configuration, a multimaster configuration. A station can transfer data to or from any other LAN station. Transmissions are half-duplex, which is typical in LANs. MOTOROLA Chapter 22. SCC HDLC Mode 22-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 786 The benefit of this configuration, however, is that full-duplex operation can be obtained. In a point-to-multipoint environment, this is the preferred configuration. Figure 22-11 shows the single-master configuration. 22-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 787 HDLC bus controller starts transmitting on the line; if a zero is detected, the internal counter is cleared. During transmission, data is continuously compared with the external bus using CTS. CTS is sampled halfway through the bit time using the rising edge of the MOTOROLA Chapter 22. SCC HDLC Mode 22-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 788 To increase performance, give the one bit more rise time by using a clock that is low longer than it is high, as shown in Figure 22-13. 22-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 789 If the transmission line driver has a one-bit delay, the delayed RTS can be used to enable the output of the line driver. As a result, the electrical effects of collisions are isolated locally. Figure 22-15 shows RTS timing. MOTOROLA Chapter 22. SCC HDLC Mode 22-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 790 CTS pin, it must be configured to connect to the chosen SCC. Because the SCC only receives clocks during its time slot, CTS is sampled only during the Tx clock edges of the particular SCC time slot. 22-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 791 Except for the above discussion in Section 22.14.6.1, “Programming GSMR and PSMR for the HDLC Bus Protocol,” use the example in Section 22.13.1, “SCC HDLC Programming Example #1.” MOTOROLA Chapter 22. SCC HDLC Mode 22-25 For More Information On This Product,...
  • Page 792 Freescale Semiconductor, Inc. HDLC Bus Mode with Collision Detection 22-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 793 In transparent mode, DLE-SYNC pairs are discarded. Normally, for proper transmission, an underrun must not occur between the DLE and its following character. This failure mode cannot occur with the MPC8280. MOTOROLA Chapter 23. SCC BISYNC Mode 23-1 For More Information On This Product,...
  • Page 794 TxBD[I]. TxBD[I] controls whether interrupts are generated after transmission of each buffer, a specific buffer, or each block. The controller then proceeds to the next BD. 23-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 795 See Section 20.1.1, “The General SCC Mode Registers (GSMR1–GSMR4).” 23.4 SCC BISYNC Parameter RAM For BISYNC mode, the protocol-specific area of the SCC parameter RAM is mapped as in Table 23-1. MOTOROLA Chapter 23. SCC BISYNC Mode 23-3 For More Information On This Product,...
  • Page 796 • The controller can be programmed so software handles the first two or three bytes. The controller directly handles subsequent data without interrupting the core. 23-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 797 Initializes receive parameters in this serial channel’s parameter RAM to reset state. Issue only when INIT RX the receiver is disabled. An resets transmit and receive parameters. PARAMETERS INIT TX AND RX PARAMETERS MOTOROLA Chapter 23. SCC BISYNC Mode 23-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 798 0x4A — CHARACTER5 0x4D — CHARACTER6 0x4E — CHARACTER7 0x50 — CHARACTER8 0x52 — MASK VALUE(RCCM) Figure 23-2. Control Character Table and RCCM 23-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 799 SYNC character is received, it discards this character if the valid bit (BSYNC[V]) is set.When using 7-bit characters with parity, the parity bit should be included in the SYNC register value. MOTOROLA Chapter 23. SCC BISYNC Mode 23-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 800 When using 7-bit characters with parity, the parity bit should be included in the DLE register value. Field Reset Undefined Addr SCC Base + 0x40 Figure 23-4. BISYNC DLE (BDLE) 23-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 801 The controller reports message transmit and receive errors using the channel BDs, error counters, and the SCCE. Modem lines can be directly monitored via the parallel port pins. Table 23-8 describes transmit errors. MOTOROLA Chapter 23. SCC BISYNC Mode 23-9 For More Information On This Product, Go to: www.freescale.com...
  • Page 802 RBCS RTR RVD DRT — Reset Addr 0x11A08 (PSMR1); 0x11A28 (PSMR2); 0x11A48 (PSMR3); 0x11A68 (PSMR4) Figure 23-5. Protocol-Specific Mode Register for BISYNC (PSMR) 23-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 803 Note: If DRT = 1, GSMR_H[CDS] should be cleared unless both of the following are true: the same clock is used for TCLK and RCLK, and CTS either has synchronous timing or is always asserted. 10–11 — Reserved, should be cleared. MOTOROLA Chapter 23. SCC BISYNC Mode 23-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 804 — — — Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer Offset + 6 Figure 23-6. SCC BISYNC RxBD 23-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 805 Carrier detect lost. Indicates when the carrier detect signal, CD, is negated during frame reception. Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” Data length represents the number of octets the CP writes into this MOTOROLA Chapter 23. SCC BISYNC Mode 23-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 806 0 Send an SYN1–SYN2 or idle sequence (specified in GSMR[RTSM]) after the last character in the buffer. 1 Send the BCS sequence after the last character. The controller also resets the BCS generator after sending the BCS. 23-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 807 BISYNC mask register (SCCM). SCCE bits are reset by writing ones; writing zeros has no effect. Unmasked bits must be reset before the CP negates the internal interrupt request signal. MOTOROLA Chapter 23. SCC BISYNC Mode 23-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 808 The real-time status of CTS and CD are part of the parallel I/O. Field — — Reset 0000_0000 Addr 0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4) Figure 23-9. SCC Status Registers (SCCS) 23-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 809 Using Table 23-15, the control character table should be set to recognize the end of the block. MOTOROLA Chapter 23. SCC BISYNC Mode 23-17 For More Information On This Product,...
  • Page 810 10. Write PRCRC with 0x0000 to comply with CRC16. 11. Write PTCRC with 0x0000 to comply with CRC16. 12. Clear PAREC for clarity. 23-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 811 ENT and ENR are enabled last. After 5 bytes are sent, the TxBD is closed. The buffer is closed after 16 bytes are received. Any received data beyond 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MOTOROLA Chapter 23. SCC BISYNC Mode 23-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 812 Freescale Semiconductor, Inc. SCC BISYNC Programming Example 23-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 813 The following list summarizes the main features of the SCC in transparent mode: • Flexible buffers • Automatic SYNC detection on receive • CRCs can be sent and received • Reverse data mode MOTOROLA Chapter 24. SCC Transparent Mode 24-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 814 TSA frames. This means that n-byte transmit buffers can be mapped directly into n-byte time slots in the TSA frames. 24-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 815 Synchronization Register (DSR).” Pattern length is specified in GSMR_H[SYNL], as shown in Table 24-1. See also Section 20.1.1, “The General SCC Mode Registers (GSMR1–GSMR4) .” MOTOROLA Chapter 24. SCC Transparent Mode 24-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 816 It is also an option to link the transmitter synchronization to the receiver synchronization. Diagrams for the pulse/envelope and sampling options are shown in Section 24.4, “Achieving Synchronization in Transparent Mode.” 24-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 817 I/O pin in software. • Enable the receiver and transmitter for the SCC in loopback mode and then change GSMR_L[DIAG] to 0b00 while the transmitter and receiver and enabled. MOTOROLA Chapter 24. SCC Transparent Mode 24-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 818 0) and from msb to lsb for bit-reversed (GSMR_H[REVD] = 1) transmission. The appended CRC is sent msb to lsb. When receiving, the CRC is calculated as the incoming 24-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 819 The current TxBD pointer (TBPTR) advances to the next TxBD in the table. Transmission resumes once TxBD[R] is set and a command is issued. RESTART TRANSMIT MOTOROLA Chapter 24. SCC Transparent Mode 24-7 For More Information On This Product,...
  • Page 820 When this occurs, the channel stops sending the buffer, closes it, sets TxBD[CT], and generates the Message TXE interrupt if it is enabled. The channel resumes sending after is received. RESTART TRANSMIT Transmission 24-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 821 — — Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 24-2. SCC Transparent Receive Buffer Descriptor (RxBD) MOTOROLA Chapter 24. SCC Transparent Mode 24-9 For More Information On This Product, Go to: www.freescale.com...
  • Page 822 Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” The Rx buffer pointer must be divisible by four, unless 24-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 823 Transmit CRC. 0 No CRC sequence is sent after this buffer. 1 A frame check sequence defined by GSMR_H[TCRC] is sent after the last byte of this buffer. MOTOROLA Chapter 24. SCC Transparent Mode 24-11 For More Information On This Product,...
  • Page 824 0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4) 0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4) Figure 24-4. SCC Transparent Event Register (SCCE)/Mask Register (SCCM) 24-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 825 RXD line. The real-time status of CTS and CD are part of the parallel I/O. Field — — Reset 0000_0000 Addr 0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4) Figure 24-5. SCC Status Register in Transparent Mode (SCCS) MOTOROLA Chapter 24. SCC Transparent Mode 24-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 826 16-bytes, so MRBLR = 0x0010. 11. Write CRC_P with 0x0000_FFFF to comply with the 16-bit CRC-CCITT. 12. Write CRC_C with 0x0000_F0B8 to comply with the 16-bit CRC-CCITT. 24-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 827 After 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received the Rx buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MOTOROLA Chapter 24. SCC Transparent Mode 24-15 For More Information On This Product,...
  • Page 828 Freescale Semiconductor, Inc. SCC2 Transparent Programming Example 24-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 829 LAN; if one is found, the station forces a jam pattern (all ones) on its frame and stops sending. Most collisions occur close to the beginning of a frame. The station waits a random period of time, called a backoff, before trying to retransmit. Once the backoff time MOTOROLA Chapter 25. SCC Ethernet Mode 25-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 830 Note that the CPM of the MPC8280 requires a minimum system clock frequency of 24 MHz to support Ethernet. 25-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 831 • Transmitter network management and diagnostics — Lost carrier sense — Underrun — Number of collisions exceeded the maximum allowed — Number of retries per frame MOTOROLA Chapter 25. SCC Ethernet Mode 25-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 832 Ethernet descriptions because it indicates when the LAN is in use. Carrier sense is defined as the logical OR of RENA and CLSN. 25-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 833 To begin transmission, the SCC in Ethernet mode (called the Ethernet controller) fetches data from the buffer, asserts TENA to the EEST, and starts sending the preamble sequence, the start frame delimiter, and frame information. If the line is busy, it waits for carrier sense MOTOROLA Chapter 25. SCC Ethernet Mode 25-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 834 (depending on PSMR[NIB]). If the two are not equal, the next bit is shifted in and the comparison is repeated. If a 25-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 835 This signal is asserted for one bit time on the second destination address bit. The CAM control logic uses RSTRT (in combination with the RXD and RCLK signals) to store the destination or source address and generate writes to the CAM for address MOTOROLA Chapter 25. SCC Ethernet Mode 25-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 836 The controller reports frame status and length in the last BD. MFLR is defined as all in-frame bytes between the start frame delimiter and the end of the frame. 25-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 837 LAN increases overall throughput by reducing the chance of collision. PSMR[SBT] offers another way to reduce the aggressiveness of the Ethernet controller. 0x7A RFBD_PTR Hword Rx first BD pointer. MOTOROLA Chapter 25. SCC Ethernet Mode 25-9 For More Information On This Product, Go to: www.freescale.com...
  • Page 838 (including the 1-byte start delimiter with the value 0xD5). 25.9 SCC Ethernet Commands Transmit and receive commands are issued to the CP command register (CPCR). Table 25-2 describes transmit commands. 25-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 839 To prevent false TENA assertions to an external transceiver, configure TENA as an input before issuing a CPM reset. See step 3 in Section 25.21, “SCC Ethernet Programming Example.” MOTOROLA Chapter 25. SCC Ethernet Mode 25-11 For More Information On This Product,...
  • Page 840 Receive Frame Ignore REJECT False True PROMISC Start Receive Discard Frame Discard Frame if REJECT is Asserted Figure 25-4. Ethernet Address Recognition Flowchart 25-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 841 25.12 Interpacket Gap Time The receiver receives back-to-back frames with a minimum interpacket spacing of 9.6 µs. In addition, after the backoff algorithm, the transmitter waits for carrier sense to be negated MOTOROLA Chapter 25. SCC Ethernet Mode 25-13 For More Information On This Product,...
  • Page 842 25.16 Handling Errors in the Ethernet Controller The Ethernet controller reports frame reception and transmission error conditions using channel BDs, error counters, and SCCE. Table 25-4 describes transmission errors. 25-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 843 CRC checking cannot be disabled, but CRC errors can be ignored if checking is not required. 25.17 Ethernet Mode Register (PSMR) In Ethernet mode, the protocol-specific mode register (PSMR), shown in Figure 25-5, is used as the Ethernet mode register. MOTOROLA Chapter 25. SCC Ethernet Mode 25-15 For More Information On This Product,...
  • Page 844 1 Receiver is not blocked when transmitter sends. Must be set for full-duplex operation. For loopback operation, GSMR[DIAG] must be programmed also; see Section 20.1.1, “The General SCC Mode Registers (GSMR1–GSMR4).” — Reserved. Should be cleared. 25-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 845 0 No SCCE[RXB] interrupt is generated after this buffer is used. 1 SCCE[RXB] or SCCE[RXF] is set when this buffer is used by the Ethernet controller. These two bits can cause interrupts if they are enabled. MOTOROLA Chapter 25. SCC Ethernet Mode 25-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 846 Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” Data length includes the total number of frame octets (including four bytes for CRC). 25-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 847 25.19 SCC Ethernet Transmit Buffer Descriptor Data is sent to the Ethernet controller for transmission on an SCC channel by arranging it in buffers referenced by the channel TxBD table. The Ethernet controller uses TxBDs to MOTOROLA Chapter 25. SCC Ethernet Mode 25-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 848 Late collision. Set when a collision occurred after the number of bytes defined for PSMR[LCW] are sent. The Ethernet controller stops sending and writes this bit after it finishes sending the buffer. 25-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 849 Graceful stop complete. Set as soon the transmitter finishes any frame that was in progress when a command was issued. It is set immediately if no frame was in progress. GRACEFUL STOP TRANSMIT MOTOROLA Chapter 25. SCC Ethernet Mode 25-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 850 P = Preamble, SFD = Start frame delimiter, DA and SA = Source/Destination address, T/L = Type/Length, D = Data, CR = CRC bytes Figure 25-10. Ethernet Interrupt Events Example 25-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 851 0x0040 to configure the physical address. 16. Clear P_PER. It is not used. 17. Clear IADDR1–IADDR4. The individual hash table is not used. 18. Clear TADDR_H, TADDR_M, and TADDR_L for clarity. MOTOROLA Chapter 25. SCC Ethernet Mode 25-23 For More Information On This Product,...
  • Page 852 TxBD is closed. Additionally, the receive buffer is closed after a frame is received. Any data received after 1520 bytes or a single frame causes a busy (out-of-buffers) condition because only one RxBD is prepared. 25-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 853 16-bit CRC-CCITT polynomial referenced in the HDLC standard protocol) are sent. The LocalTalk frame is then terminated by a flag and a restricted HDLC abort sequence. Then the transmitter’s driver is disabled. MOTOROLA Chapter 26. SCC AppleTalk Mode 26-1 For More Information On This Product,...
  • Page 854 • Reception of sync sequence does not cause extra SCCE[DCC] interrupts • Reception is automatically disabled while sending a frame • Transmit-on-demand feature expedites frames 26-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 855 The AppleTalk controller is implemented by setting certain bits in the HDLC controller. Otherwise, Chapter 22, “SCC HDLC Mode,” describes how to program the HDLC controller. Use GSMR, PSMR, or TODR to program the AppleTalk controller. MOTOROLA Chapter 26. SCC AppleTalk Mode 26-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 856 For the PSMR definition, see Section 22.8, “HDLC Mode Register (PSMR).” 26.4.3 Programming the TODR Use the transmit-on-demand (TODR) register to expedite a transmit frame. See Section 20.1.4, “Transmit-on-Demand Register (TODR).” 26-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 857 Programming the SCC in AppleTalk Mode 26.4.4 SCC AppleTalk Programming Example Except for the previously discussed register programming, use the example in Section 22.15.6, “HDLC Bus Protocol Programming.” MOTOROLA Chapter 26. SCC AppleTalk Mode 26-5 For More Information On This Product,...
  • Page 858 Freescale Semiconductor, Inc. Programming the SCC in AppleTalk Mode 26-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 859 Each wire segment is a point-to-point connection between the host and a hub or function, or a hub connected to another hub or a function. The USB transfers signal and power over a four-wire cable, and the signaling occurs over two wires and point-to-point segments. The MOTOROLA Chapter 27. Universal Serial Bus Controller 27-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 860 • Retransmission after an error and error recovery • Incrementing the frame number and generating CRC5 for the SOF (Start of Frame) token once per frame (1 ms) 27-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 861 USB reference clock must be four times the USB bit rate. Thus, USBCLK must be 48 MHz for a 12-Mbps full-speed transfer or 6 MHz for a 1.5-Mbps low-speed transfer. MOTOROLA Chapter 27. Universal Serial Bus Controller 27-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 862 The USB transmitter contains four independent FIFOs, each containing 16 bytes. There is a dedicated FIFO for each of the four supported endpoints. The USB receiver has a single 16-byte FIFO. 27-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 863 It is mandatory that endpoint 0 be configured as a control transfer type. This endpoint is used by the USB system software as a control pipe. Additional control pipes may be provided by other endpoints. MOTOROLA Chapter 27. Universal Serial Bus Controller 27-5 For More Information On This Product,...
  • Page 864 USB function controller. Reset Unenumerated Enumeration process IDLE SETUP token token token token Setup Start of frame Transmit Receive Figure 27-3. USB Controller Operating Modes 27-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 865 Host 00 (Normal) (data discarded) Data packet is sent. 01 (Ignore) — None 10 (NAK) — (data discarded) 11 (STALL) — STALL MOTOROLA Chapter 27. Universal Serial Bus Controller 27-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 866 2-4 are for function transactions in test mode. There is a dedicated FIFO for each of the four supported endpoints; endpoint 1 FIFO is for host transactions. The USB receiver has a single 16-byte FIFO. 27-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 867 LSP bit in the TxBD is set. When USMOD[TEST] is programmed, both the host state machine and function state machine are active. End points 2-4 receive/transmit data according to tokens received from MOTOROLA Chapter 27. Universal Serial Bus Controller 27-9 For More Information On This Product, Go to: www.freescale.com...
  • Page 868 27.5.1.2 Transaction-Level Interface NOTE The transaction-level interface described in this section is available only on .13 µm (HiP7) Revision A.0 and future devices. 27-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 869 The token TxBD[R] is cleared right after the OUT token transmission. USB Out Transaction Handshake Received Token Data Indication on TxBD/TrBD by Function Sent by host None None STALL STALL MOTOROLA Chapter 27. Universal Serial Bus Controller 27-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 870 The PRE token signals the hub that a low-speed transaction is about to occur. The PRE token is read only (PRE) by the hub. The USB host controller generates a full-speed PRE token before sending a packet to a low-speed peripheral. 27-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 871 USB Base + 0C RPTR Word Receive internal data pointer. Updated by the SDMA channels to show the next address in the buffer to be accessed. MOTOROLA Chapter 27. Universal Serial Bus Controller 27-13 For More Information On This Product,...
  • Page 872 BDs causes erratic operation. RBASE and TBASE values should be divisible by 8. When using the transaction-level interface in host mode, TBASE points to the TrBD ring, and RBASE is unused. 27-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 873 Offset from endpoint parameter block base. Note that the items in boldface should be initialized by the user. These parameters need not be accessed in normal operation but may be helpful for debugging. MOTOROLA Chapter 27. Universal Serial Bus Controller 27-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 874 CRC and place it in FRAME_N field. Field FRAME NUMBER CRC5 Reset — Addr USB base + 0x10 Figure 27-8. Frame Number (FRAME_N) in Host Mode—Updated by Application Software 27-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 875 The transmission order of bytes within a buffer word is reversed as compared to the Motorola mode. This mode is supported only for 32-bit port size memory. 01 PowerPC little-endian byte ordering. As data is transmitted onto the serial line from the data buffer, the least significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word.
  • Page 876 27.5.7.2 USB Slave Address Register (USADR) The USB address register is an 8-bit, memory-mapped register. It holds the address for this USB port when operating as function. 27-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 877 00 Control 00 Control /interrupt/bulk 01 Interrupt 11 Isochronous 10 Bulk 11 Isochronous 8–9 — Reserved, should be cleared. Reserved, should be cleared MOTOROLA Chapter 27. Universal Serial Bus Controller 27-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 878 RHS will be cleared by the USB function controller when a SETUP token is received. 27.5.7.4 USB Command Register (USCOM) USCOM is used to start the USB transmit operation. 27-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 879 RESET IDLE TXE4 TXE3 TXE2 TXE1 SOF BSY TXB RXB Reset 0000_0000_0000_0000 Addr 0x11B70 Figure 27-14. USB Event Register (USBER) Table 27-13 describes USBER fields. MOTOROLA Chapter 27. Universal Serial Bus Controller 27-21 For More Information On This Product, Go to: www.freescale.com...
  • Page 880 USB lines. Field — IDLE Reset 0000_0000 Addr 0x11B77 Figure 27-15. USB Status Register (USBS) Table 27-14 describes USBS fields. 27-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 881 There are up to four separate transmit BD rings and four separate receive BD rings, one for each endpoint. The BD ring allows the user to define buffers for transmission and buffers for reception. Each BD ring forms a circular queue. The CP confirms reception and MOTOROLA Chapter 27. Universal Serial Bus Controller 27-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 882 BDs to inform the processor that the buffers have been serviced. The buffers may reside in either external or internal memory. 27-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 883 FRAME STATUS DATA LENGTH RX DATA BUFFER EP4 RX BD DATA POINTER TABLE POINTER EP4 TX BD TABLE POINTER Figure 27-17. USB Memory Structure MOTOROLA Chapter 27. Universal Serial Bus Controller 27-25 For More Information On This Product, Go to: www.freescale.com...
  • Page 884 This Rx BD and its associated receive buffer are owned by the CP. Once the E-bit is set, the CPU core should not write any fields of this Rx BD. — Reserved, should be cleared 27-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 885 Overrun. A receiver overrun occurred during reception. Written by the USB controller after the received data has been placed into the associated data buffer. — Reserved, should be cleared MOTOROLA Chapter 27. Universal Serial Bus Controller 27-27 For More Information On This Product,...
  • Page 886 No fields of this BD may be written by the user once this bit is set. — Reserved, should be cleared 27-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 887 Data length (the second half word of a TxBD) is the number of octets the CP should send from this BD’s data buffer. It is never modified by the CP. MOTOROLA Chapter 27. Universal Serial Bus Controller 27-29 For More Information On This Product,...
  • Page 888 Last 0 Buffer does not contain the last byte of the message 1 Buffer contains the last byte of the message 27-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 889 Tx buffer pointer (the third and fourth half words of a TxBD) always points to the first location of the buffer in internal or external memory. The pointer may be even or odd. MOTOROLA Chapter 27. Universal Serial Bus Controller...
  • Page 890 1The TXB bit in the event register is set when this buffer is serviced. TXB can cause an interrupt if it is enabled. Last This bit should always be 1 since each TrBD represents an entire transaction. 27-32 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 891 Buffer Overflow. IN transactions only. Indicates that the number of received bytes is larger than the buffer size as provided in the Data Length field. MOTOROLA Chapter 27. Universal Serial Bus Controller 27-33 For More Information On This Product,...
  • Page 892 27.7 USB CP Commands The following transmit commands are issued to the CP command register (CPCR). Refer to Section 14.4.1, “CP Command Register (CPCR).” 27-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 893 STAL), and sets the TXE bit in the USB event register. When using the packet-level interface, the host hand will resume transmission after reception of the RESTART TRANSMIT command. shake MOTOROLA Chapter 27. Universal Serial Bus Controller 27-35 For More Information On This Product,...
  • Page 894 9. Write 0xCAFE_CAFE to DPRAM+0x200 to set up the endpoint 1 Tx data pattern. 10. Write 0xFACE_FACE to DPRAM+0x210 to set up the endpoint 2 Tx data pattern. 27-36 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 895 Programming the USB controller to act as host is similar to configuring an endpoint for function operation. A general outline of how to program the host controller follows. (A more detailed example can be found in Section 27.10.1, “USB Host Controller MOTOROLA Chapter 27. Universal Serial Bus Controller 27-37 For More Information On This Product, Go to: www.freescale.com...
  • Page 896 2 parameter RAM. 10. Write 0x0008_0028 to DPRAM+0x528 to set up the RBPTR and TBPTR fields of the endpoint 2 parameter RAM. 27-38 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 897 • RxBD[Status and Control] of the host endpoint should contain 0x3C00. • RxBD[Data Length] of the host endpoint should contain 0x0005. • The receive buffer of the host endpoint should contain 0xABCD_122B, 0x42xx_xxxx. MOTOROLA Chapter 27. Universal Serial Bus Controller 27-39 For More Information On This Product,...
  • Page 898 RAM. 7. Clear the TSTATE field of the host endpoint parameter RAM. 8. Initialize the HIMMR field of the host endpoint parameter RAM. 27-40 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 899 • TxBD[Status and Control] of endpoint 2 should contain 0x3C80. • TxBD[Data Length] of endpoint 2 should contain 0x0003. • The receive buffer of the host endpoint should contain 0xABCD_122B, 0x42xx_xxxx. MOTOROLA Chapter 27. Universal Serial Bus Controller 27-41 For More Information On This Product,...
  • Page 900 Freescale Semiconductor, Inc. Programming the USB Host Controller (Transaction-Level) 27-42 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 901 The SMC receiver and transmitter are double-buffered, corresponding to an effective FIFO size (latency) of two characters. Chapter 15, “Serial Interface with Time-Slot Assigner,” describes GCI interface configuration. MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-1 For More Information On This Product,...
  • Page 902 This mode can also be used for a fast connection between MPC8280s. • Each SMC channel fully supports the C/I and monitor channels of the GCI (IOM-2) in ISDN applications 28-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 903 Figure 28-2. SMC Mode Registers (SMCMR1/SMCMR2) Table 28-1 describes SMCMR fields. Table 28-1. SMCMR1/SMCMR2 Field Descriptions Bits Name Description — Reserved, should be cleared MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 904 1 Reverse the character bit order. The msb is sent first. SCIT channel number. (GCI) 0 SCIT channel 0 1 SCIT channel 1. Required for Siemens ARCOFI and SGS S/T chips. 28-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 905 In UART and transparent modes, the SMC’s memory structure is like the SCC’s, except that SMC-associated data is stored in buffers. Each buffer is referenced by a BD and organized in a BD table located in the dual-port RAM. See Figure 28-3. MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 906 RAM shared by the UART and transparent protocols is shown in Table 28-2. Parameter RAM for GCI protocol is described in Table 28-17. 28-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 907 A down-count value initialized with the TxBD data length and decremented with every byte the SDMA channels read. 0x24 — Word Tx temp. Can be used only by the CP. MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 908 ENTER HUNT MODE but before the command is issued and REN is set. CLOSE RXBD 28-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 909 MSB of the same double word. 1x Motorola (big-endian) byte ordering (normal operation). As data is sent onto the serial line from the buffer, the MSB of the buffer word contains data to be sent earlier than the LSB of the same word.
  • Page 910 CLOSE RXBD INIT RX PARAMETERS 4. Set SMCMR[REN]. Reception immediately uses the RxBD that RBPTR pointed to if E is set in the RxBD. 28-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 911 • Receive and transmit sections clocked at different rates • Fractional stop bits • Built-in multidrop modes • Freeze mode for implementing flow control MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 912 BD and clears R. An interrupt is issued if the I bit in the BD is set. If the next TxBD is ready, the data from its buffer is appended to the previous data and sent over 28-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 913 28.3.5 SMC UART Transmit and Receive Commands Table 28-4 describes transmit commands issued to the CPCR. MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-13 For More Information On This Product,...
  • Page 914 For 8 data bits, no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones would be sent before the first character in the buffer. If no preamble 28-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 915 • An error is received during message processing • A full receive buffer is detected • A programmable number of consecutive idle characters are received MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-15 For More Information On This Product,...
  • Page 916 Parity error. Set when a character with a parity error is received in the last byte of the buffer. A new buffer is used for additional data. The CP writes PR after received data is in the buffer. — Reserved, should be cleared. 28-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 917 Figure 28-7 shows the UART RxBD process, showing RxBDs after they receive 10 characters, an idle period, and five characters (one with a framing error). The example assumes that MRBLR = 8. MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 918 Data is sent to the CP for transmission on an SMC channel by arranging it in buffers referenced by the channel TxBD table. Using the BDs, the CP confirms transmission or 28-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 919 8-bit data, 1 start, and 1 stop, initialize the data length field to 3. To send three UART characters of 9-bit data, 1 start, and 1 stop, the data length field should 6, because the three MOTOROLA Chapter 28. Serial Management Controllers (SMCs)
  • Page 920 Reception resumes when an empty buffer is provided. 28-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 921 3. Connect BRG1 to SMC1 using the CPM mux by clearing CMXSMR[SMC1, SMC1CS]. 4. In address 0x87FC, assign a pointer to the SMC1 parameter RAM. MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-21 For More Information On This Product,...
  • Page 922 SMCMR[SM] to 0b10. Section 28.2.1, “SMC Mode Registers (SMCMR1/SMCMR2)” describes other protocol-specific bits in the SMCMR. The SMC in transparent mode does not support the following features: 28-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 923 Data is sent only during the time slots defined by the TSA. Secondly, when working with its own set of signals, the transmitter starts sending when SMSYNx is asserted. MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 924 SMC transmitter which begins sending ones asynchronously from the falling edge of SMSYN. After one character of ones is sent, if the transmit FIFO is loaded 28-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 925 Section 28.2.4, “Disabling SMCs On-the-Fly,” describes how to safely disable and reenable the SMC. Simply clearing and setting TEN may be insufficient. The receiver can also be resynchronized this way. MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-25 For More Information On This Product,...
  • Page 926 Once SMCMR[TEN] is set, the SMC waits for the transmit FIFO to be loaded before trying to achieve synchronization. When the transmit FIFO is loaded, synchronization and transmission begins depending on the following: 28-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 927 Initializes receive parameters in this serial channel to reset state. Use only if the receiver is disabled. NIT RX command resets receive and transmit parameters. PARAMETERS INIT TX AND RX PARAMETERS MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-27 For More Information On This Product, Go to: www.freescale.com...
  • Page 928 1 The buffer is empty or is receiving data. The CP owns this RxBD and its buffer. Once E is set, the core should not write any fields of this RxBD. — Reserved, should be cleared. 28-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 929 — — — Offset + 2 Data Length Offset + 4 Tx Data Buffer Pointer Offset + 6 Table 28-14. SMC Transparent TxBD MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-29 For More Information On This Product, Go to: www.freescale.com...
  • Page 930 For instance, the pointer to 8-bit transparent characters can be even or odd, but the pointer to 9-bit transparent characters must be even. The buffer can reside in internal or external memory. 28-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 931 Section 28.3.12, “SMC UART Controller Programming Example.”) 1. Configure the port D pins to enable SMTXD1, SMRXD1, and SMSYN1. Set PPARD[7,8,9] and PDIRD[9]. Clear PDIRD[7,8] and PSORD[7,8,9]. MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-31 For More Information On This Product,...
  • Page 932 GCI, one SMC can handle SCIT channel 0 and the other can handle SCIT channel 1. The main features of the SMC in GCI mode are as follows: 28-32 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 933 RSTATE, M_RxD, M_TxD, CI_RxD, and CI_TxD do not need to be accessed by the user in normal operation, and are reserved for RISC use only. 28.5.2 Handling the GCI Monitor Channel The following sections describe how the GCI monitor channel is handled. MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-33 For More Information On This Product,...
  • Page 934 RxBD and a maskable interrupt is generated. If the SMC is configured to support SCIT channel 1, the double last-look method is not used. 28-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 935 RxBD. 4–7 — Reserved, should be cleared. 8–15 DATA Data field. Contains the monitor channel data byte that the SMC received. MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-35 For More Information On This Product, Go to: www.freescale.com...
  • Page 936 DATA are always written with zeros. For C/I channel 1, bits 8–13 contain the 6-bit data field. 14–15 — Reserved, should be cleared. 28-36 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 937 CRXB MTXB MRXB Reset 0000_0000 Addr 0x11A86 (SMCE1), 0x11A96 (SMCE2)/ 0x11A8A (SMCM1), 0x11A9A (SMCM2) Figure 28-19. SMC GCI Event Register (SMCE)/Mask Register (SMCM) MOTOROLA Chapter 28. Serial Management Controllers (SMCs) 28-37 For More Information On This Product, Go to: www.freescale.com...
  • Page 938 MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer is now empty. MRXB Monitor channel buffer received. Set when the monitor receive buffer is full. 28-38 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 939 Multi-Channel Controllers (MCCs) NOTE The MPC8270 and the MPC8275 have only one MCC. Refer to www.motorola.com/semiconductors for the latest RAM microcode packages that support enhancements. A multi-channel controller (MCC) allows the MPC8280 to support up to 128 separate time-division serial channels on one peripheral. The MPC8280 has two MCCs. Each MCC is paired with a serial interface (SI), allowing the MCC to communicate over any of that SI’s 4 time-division multiplexed streams (TDM).
  • Page 940 All these parameter RAM areas are described in more detail in the following sections. 29.1.1 MCC Data Structure Organization Each MCC uses the following data structures: 29-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 941 RINTBASE0–RINTBASE4 are global MCC parameters. • Three registers (MCCE, MCCM, and MCCF) at described in Section 29.8.1, “MCC Event Register (MCCE)/Mask Register (MCCM),” and Section 29.6, “MCC Configuration Registers (MCCFx).” MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-3 For More Information On This Product,...
  • Page 942 MCC’s receive channels. Therefore, software should look for frames in all active buffer descriptor rings. This parameter does not need to be reset after an interrupt. 29-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 943 (for tables 0–4), used by the CP. The user must clear it before enabling 0x34 RINTTMP1 Word interrupts. See Section 29.8, “MCC Exceptions.” 0x38 RINTTMP2 Word 0x3C RINTTMP3 Word MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 944 0xFFFFFFFF allows transmission of all 1s before first frame of data 0x7E7E7E7E allows transmission of flags before first frame of data Note: Used in conjunction with ZISTATE and ZIDATA0. 29-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 945 29.3.1.1 Internal Transmitter State (TSTATE)—HDLC Mode Internal transmitter state (TSTATE) is a 4-byte register provides transaction parameters associated with SDMA channel accesses (like function code registers) and starts the transmitter channel. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-7 For More Information On This Product,...
  • Page 946 Section 29.8.1.1, “Interrupt Circular Table Entry.” Interrupt Entry — — IDL MRF RXF BSY RXB INTMSK — Mask Bits — Mask Bits Figure 29-3. INTMSK Mask Bits 29-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 947 To minimize useless transactions on the external bus, software should always prepare the new BD, or multiple BDs, and set BD[R] before enabling polling. Must be set. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-9 For More Information On This Product, Go to: www.freescale.com...
  • Page 948 RSTATE high byte (see Figure 29-5). When the channel is active the CP changes the value of the 3 LSBs, hence these 3 bytes must be masked if the user reads back the RSTATE. 29-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 949 (60x or local). • All TxBDs must reside on the same bus (60x or local). 29.3.2 Channel-Specific Transparent Parameters Table 29-6 describes channel-specific parameters for transparent operation. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-11 For More Information On This Product,...
  • Page 950 RBDFlags Hword RxBD flags, used by the CP (read-only for the user) 0x32 RBDCNT Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only for the user) 29-12 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 951 Section 29.3.3.2, “Channel Mode Register (CHAMR)—AAL1 CES,” for additional information. Field MODE POL SYNC — — Reset — Offset 0x1A Figure 29-6. Channel Mode Register (CHAMR)—Transparent Mode MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 952 BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4 (N is any number larger than 0). 29-14 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 953 UTSb, buffer. 0x0E, UTSc, 0x12 UTSd, The offset to the CES-specific global MCC parameter RAM for MCC1 is 0x8780. For MCC2, it is 0x8880. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 954 It is the same as the CHAMR in transparent mode with three extra CES fields in bits 13–15. Field MODE SYNC — CESM UDC UTM Reset — Offset 0x1A Figure 29-8. Channel Mode Register (CHAMR)—CES Mode 29-16 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 955 Receive queue number. Specifies the receive interrupt queue number. 00 Queue number 0 01 Queue number 1 10 Queue number 2 11 Queue number 3 MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 956 SS7 features are as follows: • Up to 128 independent communication channels (64 channels per MCC) • Independent mapping for receive and transmit 29-18 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 957 Table 29-10 describes channel-specific parameters for SS7. Note that a given parameter location may have a different definition depending on the standard used (ITU-T/ANSI or Japanese standard). MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-19 For More Information On This Product,...
  • Page 958 CRC. No more data is written into the current buffer when the MFLR violation is detected. 29-20 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 959 Signal unit error counter, user initialized to 0. Incremented each time an SU is received that contains an error. These errors are: short frame, long frame, CRC error, and non-octet aligned error. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-21 For More Information On This Product,...
  • Page 960 No reset value Offset 0x18 Field MODE1 POL IDLM — Reset No reset value Offset 0x1A Figure 29-9. Extended Channel Mode Register (ECHAMR) 29-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 961 Receive queue number. Specifies the receive interrupt queue number. 00 Queue number 0. 01 Queue number 1. 10 Queue number 2. 11 Queue number 3. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-23 For More Information On This Product, Go to: www.freescale.com...
  • Page 962 Table 29-12. Parameter Values for SUERM in Japanese SS7 Parameter Definition Value Threshold Upcount JTRDelay Length of interval (24ms) 0x2F 29-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 963 12-15 FISU_PAD Padding of the automatically transmitted FISUs. If the SEN_FISU bit is set, the CP will use the value of FISU_PAD as a number of pad character. Please refer to PAD parameter in Section 29.9.2, “Transmit Buffer Descriptor (TxBD).” MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-25 For More Information On This Product, Go to: www.freescale.com...
  • Page 964 Note: If the SS7 controller is in the octet counting mode (OCM) when SUERM_DIS is set, then if no idles (only flags/data) are received while SUERM_DIS is set, then after the host 29-26 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 965 Figure 29-11. Mask1 Format Reserved, should be cleared. Byte 5 Figure 29-12. Mask2 Format 29.3.4.4.2 Comparison State Machine The following state machine exists for filtering. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-27 For More Information On This Product, Go to: www.freescale.com...
  • Page 966 Reception of an MSU resets the filtering algorithm. Also, reception of a short frame resets filtering algorithm when SS7_OPT[SF_DIS] = 0; however, when SS7_OPT[SF_DIS] = 1 (short frames are discarded), the filtering algorithm remains unchanged. 29-28 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 967 Table 29-14 describes the channel-extra parameters. These parameters are indexed using the channel number, as described in the table. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-29 For More Information On This Product,...
  • Page 968 2 bytes. Note that an MCC channel whose FIFO is in superchannel mode consumes twice as much CPM bandwidth as a normal channel. 29-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 969 The user indicates which timeslot in a superchannel should be the first to send or receive by programming the CNT and BYT fields of the superchannelled timeslots as described in Section 15.4.3, “Programming SIx RAM Entries.” MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-31 For More Information On This Product, Go to: www.freescale.com...
  • Page 970 1. If the application required that data not be sent on this superchannel until 29-32 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 971 Regular (not first) slot of the super channel The super channel BD tables are associated with channels 1 and 2 Figure 29-15. Receiver Super Channel with Slot Synchronization Example MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-33 For More Information On This Product,...
  • Page 972 Field Group 1 Group 2 Group 3 Group 4 Reset 0000_0000 Addr 0x11B38 (MCCF1), 0x11B58 (MCCF2) Figure 29-17. SI MCC Configuration Register (MCCF) 29-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 973 The following commands, used to stop and initialize channels, are issued to the MCC by writing to CPCR as described in Section 14.4.1, “CP Command Register (CPCR).” All MCC channels must be initialized using one of the following commands before being used MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-35 For More Information On This Product, Go to: www.freescale.com...
  • Page 974 The MCC interrupt reporting scheme has two levels. The circular interrupt tables (illustrated in Figure 29-18) report channel-specific events and are masked by each 29-36 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 975 MCCM global mask register. If there was no room in the interrupt table for a new entry the corresponding queue overflow (QOVx) bit will be set in the MCCE and the interrupt information is lost although operation will continue. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-37 For More Information On This Product, Go to: www.freescale.com...
  • Page 976 — TQOV TINT GUN GOV Reset 0000_0000_0000_0000 Addr 0x11B30 (MCCE1), 0x11B50 (MCCE2)/0x11B34 (MCCM1), 0x11B54 (MCCM2) Figure 29-19. MCC Event Register (MCCE)/Mask Register (MCCM) 29-38 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 977 • Section 29.3.1.2 (HDLC mode) • Section 29.3.2.2 (transparent mode) • Section 29.3.3.1.1(AAL1 CES mode) • Section 29.3.4.1 (SS7 mode) MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-39 For More Information On This Product, Go to: www.freescale.com...
  • Page 978 Tx no data. The CP sets this flag if there is no data available to be sent to the transmitter. The transmitter sends an ABORT indication and then sends idles. 29-40 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 979 • Glitching on the TDM clock. Refer to Section 29.8.1.2.1. • Synchronization pulse (sync pulse). Refer to Section 29.8.1.2.2. • Misprogramming of SIRAM. Refer to Section 29.8.1.2.3 and Section 29.8.1.2.4. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-41 For More Information On This Product,...
  • Page 980 CPCR commands for the MCC (such as Init Tx Parameters and Init Rx Parameters) must be issued to cover all MCC channel numbers that appear in either the SIRAM or 29-42 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 981 FCC's TX or RX request may have higher priority than MCC TX or RX. When FCC1 in particular is in emergency priority mode, it will always be of higher priority than an MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-43 For More Information On This Product, Go to: www.freescale.com...
  • Page 982 BDs can be added dynamically to the BDs chain. The RxBDs chain must include at least two BDs; the TxBD chain must include at least one BDs. The MCC BDs are located in the external memory. 29-44 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 983 BD. 0 This is not the first buffer in a frame. 1 This is the first buffer in a frame. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-45 For More Information On This Product,...
  • Page 984 • Data length. Data length is the number of octets written by the CP into this BD’s data buffer. It is written by the CP when the BD is closed. When this is the last BD in the 29-46 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 985 0 No interrupt is generated after this buffer has been serviced. 1 TXB in the circular interrupt circular table entry is set when this buffer has been serviced by the MCC. This bit can cause an interrupt (if enabled). MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-47 For More Information On This Product, Go to: www.freescale.com...
  • Page 986 FISU option is required, the buffer pointer must be 4-byte aligned. The buffer must reside in external memory. This value is never modified by the CP. 29-48 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 987 11. If the user did not program a channel’s TSTATE and RSTATE in step 6 to begin data transmission and reception immediately upon having an active TDM, the user may program the start conditions at this time. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-49 For More Information On This Product, Go to: www.freescale.com...
  • Page 988 SI RAM must observe the configuration defined in MCCF (see Section 29.6, “MCC Configuration Registers (MCCFx)”). The MCCF cannot be changed while there are active channels. 29-50 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 989 CPM and bus utilization. This avoids CPM and bus activity peaks when all the channels would require CPM attention and possibly have to transfer data to/from the memory simultaneously. MOTOROLA Chapter 29. Multi-Channel Controllers (MCCs) 29-51 For More Information On This Product,...
  • Page 990 MCC channels on a particular TDM, those channels must be dynamically added to the SIRAM programming in an evenly distributed fashion over multiple TDM frames. 29-52 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 991 FCCs differ from SCCs as follows: • No DPLL support. • No BISYNC, UART, or AppleTalk/LocalTalk support. • No HDLC bus. • Ethernet support only through an MII. MOTOROLA Chapter 30. Fast Communications Controllers (FCCs) 30-1 For More Information On This Product, Go to: www.freescale.com...
  • Page 992 (RTS, CTS, and CD) through the appropriate port pins and the interrupt controller. Additional handshake signals can be supported with additional parallel I/O lines. The FCC block diagram is shown in Figure 30-1. 30-2 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 993 Each FCC contains a general FCC mode register (GFMRx) that defines common FCC options and selects the protocol to be run. The GFMRx are read/write registers cleared at reset. Figure 30-2 shows the GFMR format. MOTOROLA Chapter 30. Fast Communications Controllers (FCCs) 30-3 For More Information On This Product, Go to: www.freescale.com...
  • Page 994 • In HDLC and Transparent mode, when TCI=0, data is sent on the falling edge; when TCI=1, on the rising edge. • In Ethernet mode, when TCI=0, data is sent on the rising edge; when TCI=1, on the falling edge. 30-4 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 995 This mode is useful when connecting MPC8280 in transparent mode because it allows the RTS signal of one MPC8280 to be connected directly to the CTS signal of another MPC8280. MOTOROLA Chapter 30. Fast Communications Controllers (FCCs) 30-5 For More Information On This Product, Go to: www.freescale.com...
  • Page 996 FCC. Note that the FCC provides other tools for controlling reception—the ENTER command, command, and RxBD[E]. HUNT MODE CLOSE RXBD 30-6 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 997 Field TIREM — Reset 0000_0000 Addr 0x11390 (GFEMR1), 0x113B0(GFEMR2), 0x113D0(GFEMR3) Figure 30-3. General FCC Expansion Mode Register (GFEMR) MOTOROLA Chapter 30. Fast Communications Controllers (FCCs) 30-7 For More Information On This Product, Go to: www.freescale.com...
  • Page 998 At reset, FDSRx defaults to 0x7E7E (two HDLC flags), so it does not need to be written for HDLC mode. The FDSR contents are always sent lsb first. 30-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 999 TxBD is processed immediately after the older TxBDs are sent. Field TOD — Reset 0000_0000_0000_0000 Addr 0x11308 (FTODR1), 0x11328 (FTODR2), 0x11348 (FTODR3) Figure 30-5. FCC Transmit-on-Demand Register (FTODR) MOTOROLA Chapter 30. Fast Communications Controllers (FCCs) 30-9 For More Information On This Product, Go to: www.freescale.com...
  • Page 1000 (the wrap bit is the BD table length indicator). The remaining 32-bits contain the 32-bit address pointer to the actual buffer in memory. 30-10 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...

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