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S I M U L A T E D
C P U
F U J I T S U
F L A S H
Registers
Base Address: 000000
ports
(1) Port data registers
PDR0
7
6
Addr.: D8
P07
P06
H
PDR1
15
14
Addr.: D9
P17
P16
H
PDR2
7
6
Addr: DA
P27
P26
H
PDR3
15
14
Addr:DB
P37
P36
H
Note: R/W for I/O ports means the following:
Input mode
Read: The level at the corresponding pin is read.
Write: Data is written to an output latch, but not to the pin.
Output mode
Read: The level at the corresponding pin is read. In most cases it will be the
value written to the pin as last, the only exception can happen when the
pin is erroneously pulled hard to VCC or GND.
Write: Data is written to an output latch and output to the corresponding pin.
(2) Port direction registers
DDR0
7
Addr.: DC
D07
H
DDR1
15
Addr.: DD
D17
H
DDR2
7
Addr.: DE
D27
H
P O R T S
( P 0 ,
C P U )
for CPU native ports, 0000D8
H
5
4
3
P05
P04
P03
13
12
11
P15
P14
P13
5
4
3
P25
P24
P23
13
12
11
P35
P34
P33
6
5
4
3
D06
D05
D04
D03
14
13
12
11
D16
D15
D14
D13
6
5
4
3
D26
D25
D24
D23
62
62
62
62
P 1 ,
P 2 ,
P 3
O F
for simulated CPU
H
2
1
0
Initial
value
P02
P01
P00
00
10
9
8
Initial
value
P12
P11
P10
00
2
1
0
Initial
value
P22
P21
P20
00
10
9
8
Initial
value
P32
P31
P30
00
2
1
0
D02
D01
D00
10
9
8
D12
D11
D10
2
1
0
D22
D21
D20
Acces
s
R/W
H
Acces
s
R/W
H
Acces
s
R/W
H
Acces
s
R/W
H
Initial
Acces
value
s
00
R/W
H
Initial
Acces
value
s
00
R/W
H
Initial
Acces
value
s
00
R/W
H
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