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2.12.1 Analog Input/Output
The 56F827EVM uses jacks for line-level stereo input, line-level stereo output and stereo
headphone output. A National Semiconductor LM4880 is used to provide the drive
required for the use of headphones. This device offers a THD, which is superior to the
CS4218's on-chip headphone drive circuitry by a factor of two. The basic Analog codec
connections are shown in
2.12.2 Digital Interface
The serial interface of the codec transfers digital audio data and control data into and out
of the device. The SSI port, which consists of independent transmitter and receiver
sections, is used for serial communication with the codec.
On the hybrid controller side, the Serial Transmit Data pin, STD, is an output when data is
being transmitted to the codec. The Serial Receive Data pin, SRD, is an input when data is
being received from the codec. These two pins are connected to the codec's Serial Data
Input pin, SDIN, and Serial Data Output pin, SDOUT.
The controller's Transmit Serial Clock pin, STCK, provides the serial bit rate clock for the
SSI interface. It is connected to the codec's Serial Port Clock pin, SCLK. Data is
transmitted on the rising edge of SCLK and is received on the falling edge of SCLK.
The device's GPIO PORT D Bit 0 pin, PD0, is programmed to control the codec's Active
Low Reset signal, RESET.
2-14
Freescale Semiconductor, Inc.
56F827
Codec Enable Logic
STD
SRD
STCK
STFS
PD0
PD1
PD2
PD3
Figure 2-11. CS4218 Stereo Audio Codec
Figure
2-10.
56F827 Evaluation Module Hardware User's Manual
For More Information On This Product,
Go to: www.freescale.com
CS4218
SDIN
SDOUT
SCLK
FSYNC
RESET
CCS
CDIN
CCLK
MOTOROLA
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