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3.18 Resets
A reset causes the processor to begin executing code from the default boot location
(0xFFF0 0100). The following table shows the events that can cause a reset.
Table 3-24 Reset Causes
Source
Power-on
Watchdog time-out
CompactPCI push-button reset
CompactPCI reset
Software Generated reset
If the IMP2B is configured as the System Controller (Rack Host), then a hard reset
causes the CompactPCI backplane reset to be driven active, resetting all peripheral
cards in the system.
The cause of a reset is latched in the EPLD
Publication No. IMP2B-0HH/5
Action
Hard reset all devices
Hard reset all devices
Hard reset all devices if System Controller
Hard reset all devices if Peripheral card
Hard reset all devices
CAUTION
Integrity of SDRAM data cannot be guaranteed during hard reset, since the memory controller is reset
and SDRAM refresh disabled. Similarly, integrity of Flash or EEPROM data cannot be guaranteed if a
hard reset occurs during a Flash or EEPROM write cycle, respectively.
Configuration Register
1.
Functional Description 37
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