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5.2
.
1
Master Card ( MST ) Overview
The Master Card
provides
all common
requirements
of the
audio channel
cards
.
All CPU interface
circuitry
,
Master
Bias and
Erase
signals
and Record
Ramp signals are
incorporated into
the MST card
.
The MST is located at the
bottom of the audio card section ( under the
transport
casting
)
.
Additionally
,
the MST card
provides
the interface
to the rest of the audio
system
which
encompasses
the
Alignment
Panel
( ALN ) and audio monitor control functions in
the Remote Control Unit
.
The tasks
performed by
the MST card include the
following
:
1 ) Audio Address Bus Interface ( DWR
-
0
through 3
,
CHAN
-
0
through
7
,
PA - 0
through
7 )
2 )
Record Hold Command Generation
3
) Erase
Stagger Delay
Generation ( ERASE PULSE
O
,
ERASE
PULSE E )
4 ) Erase and Bias
Ramp
Rate Generation ( ERASE CLK
,
BIAS
CLK )
5 ) Erase and Bias
Signal
( sine wave ) Generation
6
) CAL SUM
ACN Buffer
7 ) CPU Audio Data Bus ( from the LNT board )
Loop
-
through
Interfacing
of this board with the audio
system
control
keys
on the
Remote Control Panel is
performed by
the Connector
Interface
( CNX ) board
.
5.2
.
2
MST Circuit Description
The data
provided
to the MST is in 8 bit parallel format
( ADTA
-
0
through
ADTA -
7 )
.
One half of the bits provide data
directly
.
There is also
an
8 bit parallel
audio address
bus
input to
the MST card which
provides
the
addressing to
the
3
eproms
of the
Master Card
.
This address information
is routed
to
the
eproms
IC 22
,
IC 23 and IC 24
.
These devices
are not being
used in their conventional fashion but
as
pre
-
programed
device selects
,
determining
the parameters
PA
-
0
through
PA
-
9
,
channel selects ( 1
through 3
)
.
The multitrack
audio drawer selects ( 1
through 3
)
are
used
on
the
APR -
24
Series
.
The APR
-
5000 Series will enable
only
one drawer
command
,
since there is
only one
drawer
.
Drawer 0
performs
routing
program
maintenance within the MST card
.
IC 25 C and
IC 13 B
are
ROM
Chip
Select ( CS
) devices
,
when the BCSB line
goes
low
.
The data
portion
of the 16 bits is directed from
the data
buffer
IC 27 to IC 28
,
IC 29 and IC 30
.
IC 28
provides
the REC HOLD and REC HOLD commands
,
ERS PULS and ERS PULS
clocks
,
and the ESD
-
0
through
ESD
-
3
data ( Erase
Stagger Delay
data )
.
5
-
6
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