Paragraph
16-1 OnCE Block Diagram ..................................................................................... 16-1
16-2 OnCE Controller............................................................................................. 16-2
16-9 CPU Scan Chain Register (CPUSCR) ......................................................... 16-17
16-11 OnCE PC FIFO ............................................................................................ 16-20
16-12 Recommended Connector Interface to JTAG/OnCE Port............................ 16-22
A-1
A-2
Reset Timing ....................................................................................................A-3
A-3
MOD Timing .....................................................................................................A-3
A-4
A-5
EIM Read/Write Timing ....................................................................................A-5
A-6
A-7
A-8
A-9
A-11 TRST Timing ....................................................................................................A-9
A-12 Test Access Port Timing ................................................................................A-10
B-1
144-Lead Plastic Thin Quad Flat Pack Pin Assignment...................................B-1
C-1
C-2
C-3
C-4
C-5
C-6
Reset Source Register .....................................................................................C-6
C-7
C-8
TOD Seconds Register ....................................................................................C-8
C-9
TOD Fraction Register .....................................................................................C-8
C-15 PIT Data Register...........................................................................................C-13
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LIST OF ILLUSTRATIONS
Title
For More Information On This Product,
Go to: www.freescale.com
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MOTOROLA
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