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(82) Receive section and line layer event termination Read clear Enable registers (TSLER_RCE)
This register is read clear enable register of the TSLER_RC register.
Register
Name
Port0:
TSLER_RCE
01D8
31
30
29
28
15
14
13
12
Reserved
Bit
Field
Reserved
D31-D12
Set to 0.
D11
SD
1: enable
SF
D10
1: enable
CD
D9
1: enable
Reserved
D8
Reserved
PSBF
D7
1: enable
LRDI
D6
1: enable
LAIS
D5
1: enable
D4
STIU
1: enable
STIM
D3
1: enable
LOF
D2
1: enable
OOF
D1
1: enable
D0
LOS
1: enable
CHAPTER 5 REGISTERS
Address
Port1:
Port2:
Port3:
05D8
09D8
0DD8
27
26
25
24
Reserved
11
10
9
8
SD
SF
CD
Res
0: disable
0: disable
0: disable
0: disable
0: disable
0: disable
0: disable
0: disable
0: disable
0: disable
0: disable
PRELIMINARY
Access
Default
R/W
00000FFF h
23
22
21
20
7
6
5
4
PSBF
LRDI
LAIS
STIU
Function
NEC confidential and Proprietary
Function
Read clear enable
19
18
17
16
3
2
1
0
STIM
LOF
OOF
LOS
Default
All 0
1
1
1
1
1
1
1
1
1
1
1
1
249
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