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Table 5.2 Descriptions of the TDA10021 board configuration window
Tuner configuration
Tuner type
IF frequency
Enable reading
Spectral inversion
Demodulator
BER counter depth
Equalizer
MPEG TS output1
MPEG TS output2
PLL (Set to CUSTOM under Board to enter wanted frequency and PLL factors)
Crystal frequency
PLL factors (M, N, P)
FIGURE 5.3 : TDA10021 registers under lock condition
MPEG TS status :
Disable : CONTROL register (index 2c) = 0f
Enable : CONTROL register (index 2c) = 0d (for further decoding purpose)
Select the type of tuner. If another tuner is used, select none.
Enter the IF center frequency delivered by the tuner (36.125 or 43.75Mhz).
Enable/disable to read the tuner PLL status. When enabled, the "?" mark in the main
window disappears and indicates if the PLL is locked or not. Must be disabled in normal
operation to avoid some parasitics phenomenon on the tuner.
Enter a possible spectral inversion in the tuner if it is known
Defines over many symbols the BER is measured. For BER values, the value must be set
8
to 10
to get a reliable and stable value.
Set the type of Equalizer (DFE or Linear Transversal) or disable the equalizer
Configure the MPEG TS output pins (parallel mode or serial mode)
Configure the MPEG TS output pins serial mode only delivered on the JTAG pins when
ENSERI pin is set to '1'
Specifies the Xtal frequency connected to the TDA10021
Set the different divider ratios of the PLL
15
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BU RF Solutions
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