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4 GB
CPU memory space
Figure 3-2
3 . 2 . 2
Memory Access
The priority order for control of UGM access is as follows:
1. Refreshing
2. Display
3. CPU
4. Other (command fetches, drawing, source referencing, etc.)
To enable these different kinds of processing to be performed in parallel, after performing access for
a fixed period, the Q2 passes the access right to another source. So if three sources are requesting
access, for example, they will perform accesses alternately.
UGM Access by the CPU: The CPU can access the UGM in two ways, via CPU software or
via the DMAC. When the CPU accesses the UGM, the UGM address is input directly to the Q2's
A1–A22 pins and the CS0 pin is driven low. Therefore, a UGM address in the range specified by
the memory mode register should be input to the Q2's A1–A22 pins. For example, when using
one 4-Mbit memory as the UGM, the Q2's A19–A22 pins must go low when the UGM is
accessed by the CPU.
Since an SuperH Series CPU is used, the UGM is mapped onto "SuperH external memory space
other than reserved areas (cache-through)." Data transfer between the CPU and UGM is
synchronized with the Q2's operating clock.
For UGM access by the CPU, set initial values in the interface control register, memory control
register, and display control register, and then start display synchronization operation before
UGM
Example of UGM Mapping onto CPU Memory Space
Frame buffer 0
Frame buffer 1
Source patterns
Display list
Typical uses of UGM
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