Lsi Pin Description - Yamaha A5000 Service Manual
Professional sampler
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Also See for A5000:
- Owner's manual (296 pages) ,
- Supplementary manual (25 pages) ,
- Owner's manual (27 pages)
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A5000/A4000
LSI PIN DESCRIPTION
TC203C760HF-002 (XS725A00) SWP30B (AW M Tone Generator coped with MEG) Standard W ave Processor
PIN
NAME
I/O
N O.
1
Vss
2
CA0
I
3
CA1
I
4
CA2
I
5
CA3
I
6
CA4
I
7
CA5
I
8
CA6
I
9
CA7
I
10
CA8
I
11
CA9
I
12
CA10
I
13
CA11
I
14
VSS
-
15
CD0
I/O
16
CD1
I/O
17
CD2
I/O
18
CD3
I/O
19
CD4
I/O
20
CD5
I/O
21
CD6
I/O
22
CD7
I/O
23
CD8
I/O
24
CD9
I/O
25
CD10
I/O
26
CD11
I/O
27
CD12
I/O
28
CD13
I/O
29
CD14
I/O
30
VDD
-
31
VSS
-
32
CD15
I/O
33
CSN
I
34
W RN
I
35
RDN
I
36
VDD
-
37
SYSH0
O
38
SYSH1
O
39
SYSH2
O
40
SYSH3
O
41
SYSH4
O
42
SYSH5
O
43
SYSH6
O
44
SYSH7
O
45
KONO0
O
46
KONO1
O
47
KONO2
O
48
KONO3
O
49
VSS
-
50
SYSL0
I/O
51
SYSL1
I/O
52
SYSL2
I/O
53
SYSL3
I/O
54
SYSL4
I/O
55
SYSL5
I/O
56
SYSL6
I/O
57
SYSL7
I/O
58
KONI0
I
59
KONI1
I
60
VDD
-
61
VSS
-
62
KONI2
I
63
KONI3
I
64
DAC0
O
65
DAC1
O
66
W CLK
O
67
MELO 0
O
68
MELO 1
O
69
MELO 2
O
70
MELO 3
O
71
MELO 4
O
72
MELO 5
O
73
MELO 6
O
74
MELO 7
O
75
VDD
-
76
ADLR
O
77
MELI0
I
78
MELI1
I
79
MELI2
I
80
MELI3
I
81
MELI4
I
82
MELI5
I
83
MELI6
I
84
MELI7
I
85
VSS
-
86
RCASN
O
87
RA8
O
88
RA7
O
89
RA6
O
90
VDD
-
91
VSS
-
92
RA5
O
93
RA4
O
94
RA3
O
95
RA2
O
96
RA1
O
97
RA0
O
98
RRASN
O
99
RW EN
O
100
VSS
-
101
RD7
I/O
102
RD6
I/O
103
RD5
I/O
104
RD4
I/O
105
RD3
I/O
106
RD2
I/O
107
RD1
I/O
108
RD0
I/O
109
VSS
-
110
RD17
I/O
111
RD16
I/O
112
RD15
I/O
113
RD14
I/O
114
RD13
I/O
115
RD12
I/O
116
RD11
I/O
117
RD10
I/O
118
RD9
I/O
119
RD8
I/O
120
VDD
-
10
FUN CTION
(Gr ound)
Address bus of inter nal register
(Gr ound)
Data bus of internal register
(Power supply)
(Gr ound)
Chip select
W rite strobe
Read strobe
(Power supply)
NSYS/LNSYS upper 16 bits output
Key on data
(Gr ound)
NSYS input/LNSYS output lower 8 bits
Key on data input
(Power supply)
(Gr ound)
DAC output
DAC0/DAC1 word clock
MEL wave data output
(Power supply)
ADC word clock
MEL wave data input
(Gr ound)
DRAM column address strobe (RAS signal)
(Power supply)
(Gr ound)
DRAM address bus
DRAM row address strobe (RAS signal)
DARM write enable
(Gr ound)
(Gr ound)
DRAM data bus
(Power supply)
PIN
NAME
I/O
N O.
121
VSS
-
122
HMD0
I/O
123
HMD1
I/O
124
HMD2
I/O
125
HMD3
I/O
126
HMD4
I/O
127
HMD5
I/O
128
HMD6
I/O
W ave memor y data bus (Upper 16 bits)
129
HMD7
I/O
130
HMD8
I/O
131
HMD9
I/O
132
HMD10
I/O
133
HMD11
I/O
134
HMD12
I/O
135
HMD13
I/O
136
HMD14
I/O
137
HMD15
I/O
138
VSS
-
139
HMA0
O
140
HMA1
O
141
HMA2
O
142
HMA3
O
143
HMA4
O
144
HMA5
O
145
HMA6
O
146
HMA7
O
147
HMA8
O
148
HMA9
O
149
HMA10
O
150
VDD
-
151
VSS
-
152
HMA11
O
153
HMA12
O
W ave memor y address bus
154
HMA13
O
155
HMA14
O
156
HMA15
O
157
HMA16
O
158
HMA17
O
159
HMA18
O
160
HMA19
O
161
HMA20
O
162
HMA21
O
163
HMA22
O
164
HMA23
O
165
HMA24
O
166
VSS
-
167
MRASN
O
RAS when DRAM(s ) is co nnected t o wav e mem ory
168
MCASN
O
CAS when DRAM(s ) is co nnected t o wav e mem ory
169
MOEN
O
W ave memor y output enable
170
MW EN
O
W ave memor y write enable
171
VSS
-
172
LMD0
I/O
173
LMD1
I/O
174
LMD2
I/O
175
LMD3
I/O
176
LMD4
I/O
177
LMD5
I/O
178
LMD6
I/O
179
LMD7
I/O
W ave memor y data bus (Lower 16 bits)
180
VDD
-
181
VSS
-
182
LMD8
I/O
183
LMD9
I/O
184
LMD10
I/O
185
LMD11
I/O
186
LMD12
I/O
187
LMD13
I/O
188
LMD14
I/O
189
LMD15
I/O
190
VSS
-
191
LMA0
O
192
LMA1
O
193
LMA2
O
194
LMA3
O
195
LMA4
O
196
LMA5
O
197
LMA6
O
198
LMA7
O
199
LMA8
O
200
LMA9
O
201
LMA10
O
202
LMA11
O
203
VSS
-
204
LMA12
O
205
LMA13
O
W ave memor y address bus (Lower data memory)
206
LMA14
O
207
LMA15
O
208
LMA16
O
209
LMA17
O
210
VDD
-
211
VSS
-
212
LMA18
O
213
LMA19
O
214
LMA20
O
215
LMA21
O
216
LMA22
O
217
LMA23
O
218
LMA24
O
219
VSS
-
220
SYO
O
Sync. signal for master clock
221
SYOD
O
Sync. signal for HCLK/Q CLK
222
QCLK
O
1/12 master clock (64F s)
223
HCLK
O
1/6 master clock (128F s)
224
CK256
O
1/3 master clock (256F s)
225
SYSCLK
O
1/2 master clock (384F s)
226
VDD
-
227
SYI
I
Sync. clock
228
MCLKI
I
Master clock input
229
MCLKO
O
Master clock output
230
VDD
-
231
XIN
I
Crystal osc. input
232
XOUT
O
Crystal osc. output
233
VSS
-
234
ICN
I
Initial clear
235
CHIP2
I
2 chips mode enable
236
SLAVE
I
Master/Slave select when 2 chips mode
237
TEST ON
I
238
ACIN
I
Test pin
239
DCT EST
I
240
VDD
-
(IC507)
FUN CTION
(Gr ound)
(Gr ound)
(Power supply)
(Gr ound)
(Gr ound)
(Gr ound)
(Power supply)
(Gr ound)
(Gr ound)
(Gr ound)
(Power supply)
(Gr ound)
(Gr ound)
(Power supply)
(Power supply)
(Gr ound)
(Power supply)
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