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UPP
The UPP used for TF4 is UPP8Mv1.4 with an expected change to UPP8Mv2.x, both with
8 Mbytes internal RAM. It is clocked by a 26MHz frequency from the RF-chip "Mjölner".
The 26MHz-clock frequency is internally sliced down by UPP to 13MHz. This frequency is
then inside UPP multiplied to different frequencies, i.e. 145MHz for the DSP core. The
UPP can be divided into two functional sections, Body and Brain. Body contains system
logic, and Brain contains processor subsystem including DSP, MCU, memories and Bus
Controller. The function of the Body is mainly the same as in DCT3 system Logic. The
Body is connected to Brain via RHEA bus. The Body and Brain is shown below.
The DSP inside the Brain is a Lead
DMA controller, wait state generator and a program fetch of 32-bits. Furthermore, the
DSP core has an instruction-length flexibility of 8 to 48-bits. The maximum frequency
for the DSP core is 145MHz for the Triton baseband, although the maximum frequency
for the core itself is 400 MHz. The core can do single and dual mac-operations per clock-
cycle. This means that the 6310i baseband has a maximum of 290 MIPS (mac-opera-
tions) on the DSP-core.
The DSP core has three different RAM-banks; cache RAM, dual access RAM for storing
and manipulating data and last, single access RAM for storing and manipulating SW
variables. All the RAM-banks have a 145 MHz clock and 32-bit organization. It has also
an ARM port interface, which is used for MCU/DSP message transfer (API).
Issue 2.0 Mar/2005
Company Confidential
Figure 5: UPP architecture
16–bit DSP core from TI (Texas Interments), with a
3
Copyright © 2005 Nokia Corporation.
Company Confidential
TFE-4/RV-1
TF4 Technical Information
Page 8b-15
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