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DV-600S
DV-600H
11-6. IC501 IX1539GE
Symbol
Type
DQ
/A
Input
15
-1
A
-A
Input
0
12
A
-A
Input
13
17
DQ
-DQ
Input/Output
0
7
DQ
-DQ
Input/Output
8
15
CE#
Input
RP#
Input
OE#
Input
WE#
Input
RY/BY#
Output
BYTE#
Input
Vpp
Vcc
GND
NC
• Block Diagram
FLASH
Byte selection address: When the device is in the x8 mode, the low or high order byte is
selected. It is not used in the x16 mode.
(If BYTE# is high, DQ
/A
input circuit does not operate.)
15
-1
Word selection address: Selection of one word of 16k byte block. These addresses are
latched during data wiring operation.
Block selection address: Selection of 1/32 erase block. These addresses are latched
during data writing, erasing and lock block operation.
Low order byte data input/output: Command user interface writing cycle data and command
input. Various data read memory identifier and status data output Chip nonselection or output
disable: Float state
High order byte data input/output: The function is the same as that of low order byte data
input/output. Operative only in x16 mode. x8 mode: Float state DQ
Chip enable: Device control logic, input buffer, decoder and sense amp. are activated.
Chip becomes active only when CE# is "Low".
Reset/Power down: If RP# is set to "Low", the control circuit is initialized when power is turned
on. Hence, the RP#pin is set to "Low". When power is turned on or off or in case of fluctuation it
is kept at "Low" so as to protect data from noise. When RP# is in "Low" state, the device is in
deep power down state. 480 ns is required to recover from the deep power down state. If the RP#
pin becomes "Low", the whole chip operation is interrupted and reset. After recovery the device is set
to array read state.
Output enable: When OE# is set to "Low", data is output from the DQ pin. When OE# is
set to "High", the DQ pin is set to float state.
Write enable: Command user interface, data Q register and address Q latch access is controlled.
In "Low" state WE# becomes active. At rise edge the address and data are fetched.
Ready/busy: The state of internal write state machine is output. In "Low" state it is indicated that the
write state machine is in operation. If the write state machine waits for next operation instruction, erase
is suspended or it is in deep power down state, the RY/BY# pin is in float state.
Byte enable: When BYTE# is set to "Low", the device is set to the x8 mode. At this time the
DQ
-DQ
pin becomes float state. Address A
8
15
When BYTE# is "High", the device is set to the x16 mode. The A
Write/erase power supply: 5.0 ± 0.5V is applied during writing/erasing.
Device power supply: 5.0 ± 0.5V
Ground
Nonconnection
DQ
8-15
Output
Buffer
Input
Buffer
Y-DECODER
ADDRESS
QUEUE
LATCHES
X-DECODER
ADDRESS
COUNTER
Name and function
selects high order/low order byte.
-1
DQ
0-7
Output
Input
Input
Buffer
Buffer
Buffer
I/O Logic
DATA
QUEUE
ID
REGISTER
Register
CSR
Register
ESRs
Data
Comparator
Y GATING/SENSING
Program Erase
Voltage Switch
11-7
/A
is address.
15
-1
input circuit is disabled.
-1
BYTE#
CE#
OE#
WE#
RP#
RY/BY#
V
PP
V
CC
GND
- Quick Links:
- Specifications
- Wiring Diagram
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