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3DQDVRQLF
* IF-amplifier
The IF-amplifier has symmetrical inputs and consists of three AC coupled differential gain stages with
AGC function. Due to the AC coupling, biasing is simple so that cascades can be used and no DC
feedback is necessary. The gain control range of the IF amplifier is 64dB minimal. The input sensitivity
for AGC onset is 70 mV typical. The maximal IF-gain can be reduced with 20dB by means of I²C bus
IFS.
* PLL-demodulator and alignment free VCO
The IF-signal is demodulated with the help of a PLL detector. The PLL detector is used to regenerate a
reference signal that is in phase to the IF-carrier signal. Demodulation is achieved by multiplying this
reference signal with the incoming IF-signal. This reference signal is a clean signal that does not
contain video information; this bandwidth (approx. 60kHz) is determined by the PLL loopfilter pin 5.
The demodulator can handle both negative and negative modulation, selection is done with I²C bus bit
MOD.
A low pass filter after the demodulator output reduces the higher frequency demodulation products.
The voltage controlled oscillator, VCO, is alignment free and makes the concept even more attractive.
No external coil is required any more. It saves both the coil costs and an alignment. As regards EMC
the system becomes more robust. The required IF-system frequency 38.9, 45.75MHz, including
SECAM-L', is selected by I²C. The correct VCO frequency is determined by the calibrator system
which uses one of the actual chroma crystal as reference. Calibration occurs automatically after
power-on and every time after loss of sync lock (I
The PLL catching range is plus/min 1MHz around the selected IF-frequency. Within this range the PLL
ensures automatic tracking to the incoming frequency. The PLL is basically an "FPLL", Frequency
Phase Lock Loop system. This extra frequency detector gives an output signal to the PLL loopfilter as
long as a difference in frequency is detected. This ensures fast catching.
The PLL loopfilter time constant can be made fast via Fast Filter IF-PLL, FFI. This function has been
made available to handle RF-transmitter signals with large phase modulation (for special market
areas).
* Video buffer
The video buffer is required to provide a low ohmic video output with the right amplitude and to protect
this output for the occurrence of noise peaks, refer to figure below. The video buffer also contains a
level shifter and gain stage for positive and negative modulation in order to provide a correct video
amplitude and DC level.
The video buffer bandwidth is typical 9 MHz. The video output amplitude is 2.2Vpp (sync inclusive),
independent of the supply voltage. A white spot clamp prevents the video amplitude becoming greater
than 5.3V typical. A noise clamp prevents the video output becoming less than 1.7V typical. (Top sync
is approx. 2V) For strong signal only, the noise peak is inverted to black level.
Video out
[V]
5
zero level
4
3
2
top sync.
1
The IF part can be switched-off by means of I²C bus command VSW. The internal CVBS input than
can be used (with minimum components) as external input, for instance for satellite.
Negative
Fig 1: Video signal for negative and positive modulation
2
C bit SL)
white spot clamp
noise inv. clamp
4
top white
zero level
Positive
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