Sony DTC-670 Service Manual page 51
Digital audio tape deck
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Also See for DTC-670:
- Operating instructions manual (42 pages) ,
- Operating instructions manual (41 pages)
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lGl62 Pulse D/A Converter (CXD2561M-l)
The Converter is asmall, high-performance
I bitpulse D/A convener
that provides 4 asymmetrical PWM wave ouçuts in each ch of L/R.
1G363 Digital Filter (CXD2560M)
The Filter is a digital audio 8x oversampling
digital filter rvith builtin
LÂ 2ch filter, noise shapinganenuator,
softmutin-e deemphasis,
etc.
Pin No.
Pin Name
vo
Description
J
I
2
4
5
DVoo
TEST
INIT
LRCKI
DRI
I
I
I
I
Digital power supply
Test terminal. Normally fixed
ar "L."
Again synchronized at the
buildup edge of the signal.
LRCK input
Rch data inout
6
7
8
9
l 0
DLI
BCKI
DVss
5 l 2 F s
XVss
o
I
I
Lch data input
BCK input
Digital GND
5l2Fs ouçut
Clock GND
l l
I L
l 3
t 4
l 5
XIN
XOUT
XVoo
VSUB
AVooR
I
:
X'tal oscillator input terminal
(5 I 2Fs)
X'tal oscillator output terminal
Clock power supply
Substrate. Connected to GND.
Analog power supply
l 6
l 1
1 8
l 9
20
Rl (+)
AVssR
Rl (-)
R2 (+)
R2 (-)
o
o
o
o
Rch PLM output I
(normal phase)
Analog GND
Rch PLM output I
(reverse phase)
Rch PLM output 2
(normal phase)
Rch PLM output 2
(reverse phase)
2 l
22
23
24
25
AVoo
AVss
L2(-)
L2 (+)
Ll (-)
o
o
o
Analog power supply
Analog GND
Lch PLM ourput 2
(reverse phase)
Lch PLM output 2
(normal phase)
Lch PLM output i
(reverse phase)
26
27
28
AVssL
L l ( + )
AVooL
o
Analog GND
Lch PLM ourput I
(normal phase)
Analog power supply
Pin No.
Pin Name
vo
Description
I
2
J
1
5
Vss
SYSM
ATT
SHIFT
LATCH
I
I
I
I
Power lerminal (GND)
System mute input.
Effective upon "H"
ATT data input in CTL "L."
EMP input upon CTL "H."
Shift clock input upon CTL "L."
FS32 input upon CTL "H."
Latch clock input upon CTL
"L." FS48 input upon CTL "H."
6
7
8
9
l 0
CTL
INIT
BCKI
DATAI
LRCKI
I
I
I
Pull-down in the IC. Direct input
mode upon "H." Serial transfer
mode upon "L."
SynchronÈed again at the
buildup edge of the signal.
BCK input
Data input
LRCK input
2
4
5
TEST
Vss
l28Fs
INVI
INVO
I
o
I
o
Test terminal. Fixed at "L"
during normal use.
Power terminal (GND)
l28Fs clock ourput
Invener input
Inverter output
6
7
8
9
t0
INVO2
MCLK
Voo
BCKO
DL
o
I
o
o
Inverter output
Master clock input (f=-51 2Fs)
Power terminal (+5 V)
BCK output
Lch dara ourput
2 l
22
L3
24
DR
LRCKO
FLCL
FLGR
o
o
o
o
Rch data ourput
LRCK output
Lch o mute flag output
Rch O mute fla-e ourput
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