Table of Contents
Advertisement
LH79524/LH79525 User's Guide
In 12 or 16-bit-per-pixel Mode, the CLCDC uses the unpacked data directly to generate the
pixel value. In all other bit-per-pixel modes, the CLCDC uses the unpacked data to index its
palette RAM; the CLCDC uses the value indexed from the palette to generate the pixel value.
For STN displays, this value passes to the gray-scaling generator. For TFT displays, this
value bypasses the gray-scaling generator and goes directly to the output display drivers.
The CLCDC generates a single combined interrupt to the Vectored Interrupt Controller
(VIC) when an individual interrupt condition becomes true for upper/lower panel DMA
FIFO underflow, base address update signification, vertical compare, or bus error.
4.3.1 Supported Displays and Panels
The CLCDC retrieves image data from system memory (the frame buffer), formats the data
for the LCD panel, and writes the data to the panel. The CLCDC also creates the control
signals that cause the panel to display the formatted data.
The CLCDC translates pixel-coded data into the formats and timings required to drive:
• Single monochrome panels
• Dual monochrome panels
• Color LCD panels
• Super Twisted Nematic (STN) displays
• Active Thin Film Transistor (TFT) LCD displays.
4.3.2 Frame Buffer
A set of numbers representing the color or gray scale of each pixel the CLCDC displays is
stored in a region of static memory called a frame buffer. The CLCDC uses its DMA Con-
troller to fetch data from the frame buffer into its FIFO (or FIFOs for dual-panel interfaces)
when the amount of pixel data falls below the FIFO watermark.
Data moves from the frame buffer into the FIFO via the AHB. The frame buffer can reside
on either the external memory bus or on the internal SRAM.
4.3.3 LCD DMA FIFOs
The CLCDC has an upper LCD DMA FIFO and a lower LCD DMA FIFO. These FIFOs can
be independently controlled to cover single- and dual-panel LCDs. Each FIFO is 16 words
deep by 32 bits wide. In single-panel modes the LCD DMA FIFOs are made to appear as
a single FIFO of twice the size.
The watermarks within each FIFO are set so that each FIFO requests data when the level
of data in a FIFO falls below the programmed watermark (either four or eight locations, as
specified by bit [16] of the LCD Panel Pixel Parameter Register). An interrupt signal is
asserted, if enabled, if either of the two LCD DMA FIFOs is read when they are empty.
Color Liquid Crystal Display Controller
Version 1.0
4-5
Advertisement
Table of Contents
