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RM-356
System Module and User Interface
TV out interface
The TV-out interface is implemented using the D2480 TV-out graphics engine that provides a direct support
for TVout. The input data interface for D2480 is a 8-bit MeSSI (Medium Speed Screen Interface) parallel
command/data display interface from D2800.
The global supply voltages are VIO from N2300 and VAUX from N2200. VCORE and VPLL supply voltages are
regulated with N2498 using VIO and supply voltage from battery VBAT. The D2480 reset and regulator AV
video control signals are taken from N2850.
For TV out the D2480 supports composite video output (CVBS) and NTSC or PAL output standards. CVBS is
single video signal containing all of the necessary information to reproduce a color picture. The video signal
is connected to an external AV connector pin 3. Switch N2122 is used to connect AV connector pin 3 into TV
out and the same pin is used also as a microphone line.
Camera concept
Imaging characteristics
The imaging and video baseband subsystem contains the complete imaging system for the cameras. The
main features of the imaging and video baseband subsystem are:
• Hardware acceleration for image processing
• Support for the 3 megaixel main camera
• Support for secondary VGA camera module
• Support for Flash LEDs and its driver from ADI
Key components
DM500 imaging accelerator (N1400)
The imaging video baseband is implemented using the DM500 processor. The DM500 processor is a hardware
accelerator for imaging and video applications. This processor controls all the cameras and flashes in the
system.
This processor is controlled by Rapido via SPI interface. The boot code is downloaded into DM500 internal
memory via the SPI interface at power on. Further application code (self test, image capture, video capture)
is transferred depending on the usage case.
Video and still image data is passed to the Rapido for display & storage after processing over a CCP bus
(CCP_CMT).
3 megapixel main camera
Issue 1
Figure 61 Block diagram of TV out connection
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